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    Serialization floors and deadline driven control for performance optimization of asymmetric multiprocessor systems
    21.
    发明授权
    Serialization floors and deadline driven control for performance optimization of asymmetric multiprocessor systems 有权

    公开(公告)号：US11023245B2

    公开(公告)日：2021-06-01

    申请号：US16376828

    申请日：2019-04-05

    Applicant: Apple Inc.

    Inventor： Aditya Venkataraman ,  Bryan R. Hinch ,  John G. Dorsey

    IPC: G06F9/38 ,  G06F1/3228 ,  G06F1/3296 ,  G06F9/48 ,  G06F9/50

    Abstract: Closed loop performance controllers of asymmetric multiprocessor systems may be configured and operated to improve performance and power efficiency of such systems by adjusting control effort parameters that determine the dynamic voltage and frequency state of the processors and coprocessors of the system in response to the workload. One example of such an arrangement includes applying hysteresis to the control effort parameter and/or seeding the control effort parameter so that the processor or coprocessor receives a returning workload in a higher performance state. Another example of such an arrangement includes deadline driven control, in which the control effort parameter for one or more processing agents may be increased in response to deadlines not being met for a workload and/or decreased in response to deadlines being met too far in advance. The performance increase/decrease may be determined by comparison of various performance metrics for each of the processing agents.

    Performance telemetry aided processing scheme
    22.
    发明授权
    Performance telemetry aided processing scheme 有权

    公开(公告)号：US10942850B2

    公开(公告)日：2021-03-09

    申请号：US16513225

    申请日：2019-07-16

    Applicant: Apple Inc.

    Inventor： John G. Dorsey ,  Aditya Venkataraman ,  Bryan R. Hinch ,  Daniel A. Chimene ,  Andrei Dorofeev ,  Constantin Pistol

    IPC: G06F12/00 ,  G06F12/0802

    Abstract: A processing system can include a plurality of processing clusters. Each processing cluster can include a plurality of processor cores and a last level cache. Each processor core can include one or more dedicated caches and a plurality of counters. The plurality of counters may be configured to count different types of cache fills. The plurality of counters may be configured to count different types of cache fills, including at least one counter configured to count total cache fills and at least one counter configured to count off-cluster cache fills. Off-cluster cache fills can include at least one of cross-cluster cache fills and cache fills from system memory. The processing system can further include one or more controllers configured to control performance of one or more of the clusters, the processor cores, the fabric, and the memory responsive to cache fill metrics derived from the plurality of counters.

    PROCESSOR UNIT EFFICIENCY CONTROL
    25.
    发明申请
    PROCESSOR UNIT EFFICIENCY CONTROL 审中-公开

    公开(公告)号：US20170357302A1

    公开(公告)日：2017-12-14

    申请号：US15275213

    申请日：2016-09-23

    Applicant: Apple Inc.

    Inventor： John G. Dorsey ,  Christopher W. Chaney ,  Norman J. Rohrer ,  Cyril De La Cropte De Chanterac

    IPC: G06F1/32

    CPC classification number: G06F1/3287 ,  G06F1/3206 ,  G06F1/324 ,  Y02D10/171

    Abstract: Embodiments provide for a computer implemented method comprising sampling one or more power and performance metrics of a processor; determining an energy cost per instruction based on the one or more power and performance metrics; determining an efficiency metric based on the energy cost per instruction; computing an efficiency control error based on a difference between a current efficiency metric and a target efficiency metric; setting an efficiency control effort based on the efficiency control error; determining a performance control effort, the performance control effort determined by a performance controller for the processor; and adjusting the performance control effort based on the efficiency control effort, wherein adjusting the performance control effort reduces power consumption of the processor.

    PORTABLE ELECTRONIC DEVICE WITH PROXIMITY-BASED CONTENT SYNCHRONIZATION
    26.
    发明申请
    PORTABLE ELECTRONIC DEVICE WITH PROXIMITY-BASED CONTENT SYNCHRONIZATION 有权
    具有基于内容同步的便携式电子设备

    公开(公告)号：US20130173315A1

    公开(公告)日：2013-07-04

    申请号：US13689594

    申请日：2012-11-29

    Applicant: Apple Inc.

    Inventor： John G. Dorsey

    IPC: H04B7/26 ,  G06Q50/30 ,  G06Q10/02

    CPC classification number: H04B7/26 ,  G06F17/30035 ,  G06Q10/02 ,  G06Q30/0268 ,  G06Q50/30

    Abstract: Systems are provided that support millimeter-wave wireless communications between hosts and electronic devices. A host may be formed using a personal computer associated with a user or computing equipment associated with a public establishment. Content can be automatically synchronized between the host and the user's electronic device over a millimeter-wave wireless communications link in a communications band such as a 60 GHz wireless communications band. Synchronization operations may be performed based on user content preferences. Content preference information may be gathered explicitly from a user using on-screen options or may be gathered by monitoring user media playback activities and media rating activities. The content preference information may be transmitted automatically from an electronic device to a host when the electronic device is brought within range of the host. Synchronization operations may be performed automatically when a user is in proximity of a point-of-sale terminal or ticketing equipment.

    Abstract translation: 提供支持主机和电子设备之间的毫米波无线通信的系统。 可以使用与用户相关联的个人计算机或与公共机构相关联的计算设备来形成主机。 内容可以通过诸如60GHz无线通信频带的通信频带中的毫米波无线通信链路在主机和用户的电子设备之间自动同步。 可以基于用户内容偏好来执行同步操作。 可以使用屏幕选项从用户显式收集内容偏好信息，或者可以通过监视用户媒体播放活动和媒体评级活动来收集内容偏好信息。 当电子设备进入主机的范围内时，内容偏好信息可以从电子设备自动发送到主机。 当用户位于销售点终端或票务设备附近时，可以自动执行同步操作。

    Adaptive memory performance control by thread group
    27.
    发明授权
    Adaptive memory performance control by thread group 有权

    公开(公告)号：US11709748B2

    公开(公告)日：2023-07-25

    申请号：US17098262

    申请日：2020-11-13

    Applicant: Apple Inc.

    Inventor： John G. Dorsey ,  Andrei Dorofeev ,  Keith Cox

    IPC: G06F11/30 ,  G06F11/07 ,  G06F11/34 ,  G06F9/50

    CPC classification number: G06F11/3024 ,  G06F9/5094 ,  G06F11/076 ,  G06F11/3058 ,  G06F11/3409

    Abstract: A device implementing adaptive memory performance control by thread group may include a memory and at least one processor. The at least one processor may be configured to execute a group of threads on one or more cores. The at least one processor may be configured to monitor a plurality of metrics corresponding to the group of threads executing on one or more cores. The metrics may include, for example, a core stall ratio and/or a power metric. The at least one processor may be configured to determine, based at least in part on the plurality of metrics, a memory bandwidth constraint with respect to the group of threads executing on the one or more cores. The at least one processor may be configured to, in response to determining the memory bandwidth constraint, increase a memory performance corresponding to the group of threads executing on the one or more cores.

    Closed loop CPU performance control
    28.
    发明授权
    Closed loop CPU performance control 有权

    公开(公告)号：US11062673B2

    公开(公告)日：2021-07-13

    申请号：US16587582

    申请日：2019-09-30

    Applicant: Apple Inc.

    Inventor： John G. Dorsey ,  James S. Ismail ,  Keith Cox ,  Gaurav Kapoor

    IPC: G06F1/26 ,  G06G5/00 ,  G06T1/20 ,  G09G5/00 ,  G09G5/18 ,  G06F1/324 ,  G06F1/3296 ,  G06T1/60 ,  G06F1/20 ,  G06T13/80

    Abstract: The invention provides a technique for targeted scaling of the voltage and/or frequency of a processor included in a computing device. One embodiment involves scaling the voltage/frequency of the processor based on the number of frames per second being input to a frame buffer in order to reduce or eliminate choppiness in animations shown on a display of the computing device. Another embodiment of the invention involves scaling the voltage/frequency of the processor based on a utilization rate of the GPU in order to reduce or eliminate any bottleneck caused by slow issuance of instructions from the CPU to the GPU. Yet another embodiment of the invention involves scaling the voltage/frequency of the CPU based on specific types of instructions being executed by the CPU. Further embodiments include scaling the voltage and/or frequency of a CPU when the CPU executes workloads that have characteristics of traditional desktop/laptop computer applications.

    Performance Telemetry Aided Processing Scheme
    30.
    发明申请
    Performance Telemetry Aided Processing Scheme 有权

    公开(公告)号：US20210019258A1

    公开(公告)日：2021-01-21

    申请号：US16513225

    申请日：2019-07-16

    Applicant: Apple Inc.

    Inventor： John G. Dorsey ,  Aditya Venkataraman ,  Bryan R. Hinch ,  Daniel A. Chimene ,  Andrei Dorofeev ,  Constantin Pistol

    IPC: G06F12/0802

    Abstract: A processing system can include a plurality of processing clusters. Each processing cluster can include a plurality of processor cores and a last level cache. Each processor core can include one or more dedicated caches and a plurality of counters. The plurality of counters may be configured to count different types of cache fills. The plurality of counters may be configured to count different types of cache fills, including at least one counter configured to count total cache fills and at least one counter configured to count off-cluster cache fills. Off-cluster cache fills can include at least one of cross-cluster cache fills and cache fills from system memory. The processing system can further include one or more controllers configured to control performance of one or more of the clusters, the processor cores, the fabric, and the memory responsive to cache fill metrics derived from the plurality of counters.

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