公开(公告)号：US20230169003A1

公开(公告)日：2023-06-01

申请号：US18160575

申请日：2023-01-27

Applicant: Apple Inc.

Inventor： James Vash ,  Gaurav Garg ,  Brian P. Lilly ,  Ramesh B. Gunna ,  Steven R. Hutsell ,  Lital Levy-Rubin ,  Per H. Hammarlund ,  Harshavardhan Kaushikkar

IPC: G06F12/0815 ,  G06F12/0831

CPC classification number: G06F12/0815 ,  G06F12/0831 ,  G06F2212/1032

Abstract: A scalable cache coherency protocol for system including a plurality of coherent agents coupled to one or more memory controllers is described. The memory controller may implement a precise directory for cache blocks from the memory to which the memory controller is coupled. Multiple requests to a cache block may be outstanding, and snoops and completions for requests may include an expected cache state at the receiving agent, as indicated by a directory in the memory controller when the request was processed, to allow the receiving agent to detect race conditions. In an embodiment, the cache states may include a primary shared and a secondary shared state. The primary shared state may apply to a coherent agent that bears responsibility for transmitting a copy of the cache block to a requesting agent. In an embodiment, at least two types of snoops may be supported: snoop forward and snoop back.

公开(公告)号：US20230064526A1

公开(公告)日：2023-03-02

申请号：US17657506

申请日：2022-03-31

Applicant: Apple Inc.

Inventor： Sagi Lahav ,  Lital Levy - Rubin ,  Gaurav Garg ,  Gerard R. Williams, III ,  Samer Nassar ,  Per H. Hammarlund ,  Harshavardhan Kaushikkar ,  Srinivasa Rangan Sridharan ,  Jeff Gonion

IPC: G06F9/46 ,  G06F13/16

Abstract: Techniques are disclosed relating to an I/O agent circuit. The I/O agent circuit may include one or more queues and a transaction pipeline. The I/O agent circuit may issue, to the transaction pipeline from a queue of the one or more queues, a transaction of a series of transactions enqueued in a particular order. The I/O agent circuit may generate, at the transaction pipeline, a determination to return the transaction to the queue based on a detection of one or more conditions being satisfied. Based on the determination, the I/O agent circuit may reject, at the transaction pipeline, up to a threshold number of transactions that issued from the queue after the transaction issued. The I/O agent circuit may insert the transaction at a head of the queue such that the transaction is enqueued at the queue sequentially first for the series of transactions according to the particular order.

公开(公告)号：US20230056044A1

公开(公告)日：2023-02-23

申请号：US17821296

申请日：2022-08-22

Applicant: Apple Inc.

Inventor： Per H. Hammarlund ,  Lior Zimet ,  James Vash ,  Gaurav Garg ,  Sergio Kolor ,  Harshavardhan Kaushikkar ,  Ramesh B. Gunna ,  Steven R. Hutsell

IPC: G06F13/28 ,  G06F12/0815 ,  G06F12/109

Abstract: A system including a plurality of processor cores, a plurality of graphics processing units, a plurality of peripheral circuits, and a plurality of memory controllers is configured to support scaling of the system using a unified memory architecture.

公开(公告)号：US20250015701A1

公开(公告)日：2025-01-09

申请号：US18893579

申请日：2024-09-23

Applicant: Apple Inc.

Inventor： Alexander B. Uan-Zo-li ,  Shuai Jiang ,  Jamie L. Langlinais ,  Per H. Hammarlund ,  Hans L. Yeager ,  Victor Zyuban ,  Sung J. Kim ,  Wei Xu ,  Rohan U. Mandrekar ,  Sambasivan Narayan ,  Mohamed H. Abu-Rahma ,  Jaroslav Raszka ,  Robert O. Bruckner

IPC: H02M1/00

Abstract: A power delivery sub-system included in a computer system employs a primary voltage regulator circuit that generates a primary supply voltage on a primary power supply node. The power delivery sub-system also includes multiple bypass voltage regulator circuits that source corresponding bypass currents to a local power supply nodes in an integrated circuit. The integrated circuit includes multiple circuit blocks coupled to corresponding ones of the local power supply nodes, and multiple local voltage regulator circuits coupled to the primary power supply node. When a voltage level of a given local power supply node drops below a threshold value, a corresponding local voltage regulator circuit sources a supply current to the given local power supply node.

公开(公告)号：US20240273024A1

公开(公告)日：2024-08-15

申请号：US18582333

申请日：2024-02-20

Applicant: Apple Inc.

Inventor： James Vash ,  Gaurav Garg ,  Brian P. Lilly ,  Ramesh B. Gunna ,  Steven R. Hutsell ,  Lital Levy-Rubin ,  Per H. Hammarlund ,  Harshavardhan Kaushikkar

IPC: G06F12/0815 ,  G06F12/0831

CPC classification number: G06F12/0815 ,  G06F12/0831 ,  G06F2212/1032

Abstract: A scalable cache coherency protocol for system including a plurality of coherent agents coupled to one or more memory controllers is described. The memory controller may implement a precise directory for cache blocks from the memory to which the memory controller is coupled. Multiple requests to a cache block may be outstanding, and snoops and completions for requests may include an expected cache state at the receiving agent, as indicated by a directory in the memory controller when the request was processed, to allow the receiving agent to detect race conditions. In an embodiment, the cache states may include a primary shared and a secondary shared state. The primary shared state may apply to a coherent agent that bears responsibility for transmitting a copy of the cache block to a requesting agent. In an embodiment, at least two types of snoops may be supported: snoop forward and snoop back.

公开(公告)号：US12007895B2

公开(公告)日：2024-06-11

申请号：US17821305

申请日：2022-08-22

Applicant: Apple Inc.

Inventor： Per H. Hammarlund ,  Eran Tamari ,  Lior Zimet ,  Sergio Kolor ,  Sergio V. Tota ,  Sagi Lahav ,  James Vash ,  Gaurav Garg ,  Jonathan M. Redshaw ,  Steven R. Hutsell ,  Harshavardhan Kaushikkar ,  Shawn M. Fukami

IPC: G06F12/08 ,  G06F12/0811 ,  G06F12/0815 ,  G06F12/0831 ,  G06F12/109 ,  G06F12/128 ,  G06F13/16 ,  G06F13/28 ,  G06F13/40 ,  G06F15/173 ,  G06F15/78

CPC classification number: G06F12/0831 ,  G06F12/0811 ,  G06F12/0815 ,  G06F12/109 ,  G06F12/128 ,  G06F13/161 ,  G06F13/1668 ,  G06F13/28 ,  G06F13/4068 ,  G06F15/17368 ,  G06F15/7807 ,  G06F2212/305 ,  G06F2212/657

Abstract: A system including a plurality of processor cores, a plurality of graphics processing units, a plurality of peripheral circuits, and a plurality of memory controllers is configured to support scaling of the system using a unified memory architecture.

公开(公告)号：US11972140B2

公开(公告)日：2024-04-30

申请号：US18069033

申请日：2022-12-20

Applicant: Apple Inc.

Inventor： Steven Fishwick ,  Jeffry E. Gonion ,  Per H. Hammarlund ,  Eran Tamari ,  Lior Zimet ,  Gerard R. Williams, III

IPC: G06F3/06 ,  G06F12/02 ,  G06F12/06 ,  G06F12/0871 ,  G06F12/0882 ,  G06F12/1018 ,  G06F12/1045 ,  G06F13/16

CPC classification number: G06F3/0655 ,  G06F3/0604 ,  G06F3/0683 ,  G06F12/0238 ,  G06F12/0646 ,  G06F12/0871 ,  G06F12/0882 ,  G06F12/1018 ,  G06F12/1054 ,  G06F12/1063 ,  G06F13/1668

Abstract: In an embodiment, a system may support programmable hashing of address bits at a plurality of levels of granularity to map memory addresses to memory controllers and ultimately at least to memory devices. The hashing may be programmed to distribute pages of memory across the memory controllers, and consecutive blocks of the page may be mapped to physically distant memory controllers. In an embodiment, address bits may be dropped from each level of granularity, forming a compacted pipe address to save power within the memory controller. In an embodiment, a memory folding scheme may be employed to reduce the number of active memory devices and/or memory controllers in the system when the full complement of memory is not needed.

公开(公告)号：US20240063715A1

公开(公告)日：2024-02-22

申请号：US17820168

申请日：2022-08-16

Applicant: Apple Inc.

Inventor： Alexander B. Uan-Zo-li ,  Shuai Jiang ,  Jamie L. Langlinais ,  Per H. Hammarlund ,  Hans L. Yeager ,  Victor Zyuban ,  Sung J. Kim ,  Wei Xu ,  Rohan U. Mandrekar ,  Sambasivan Narayan ,  Mohamed H. Abu-Rahma ,  Jaroslav Raszka ,  Robert O. Bruckner

IPC: H02M3/07 ,  H02M1/00

CPC classification number: H02M3/07 ,  H02M1/0067

Abstract: A power delivery sub-system included in a computer system employs a primary voltage regulator circuit that generates a primary supply voltage on a primary power supply node. The power delivery sub-system also includes multiple bypass voltage regulator circuits that source corresponding bypass currents to a local power supply nodes in an integrated circuit. The integrated circuit includes multiple circuit blocks coupled to corresponding ones of the local power supply nodes, and multiple local voltage regulator circuits coupled to the primary power supply node. When a voltage level of a given local power supply node drops below a threshold value, a corresponding local voltage regulator circuit sources a supply current to the given local power supply node.

公开(公告)号：US11868258B2

公开(公告)日：2024-01-09

申请号：US18160575

申请日：2023-01-27

Applicant: Apple Inc.

Inventor： James Vash ,  Gaurav Garg ,  Brian P. Lilly ,  Ramesh B. Gunna ,  Steven R. Hutsell ,  Lital Levy-Rubin ,  Per H. Hammarlund ,  Harshavardhan Kaushikkar

IPC: G06F12/0815 ,  G06F12/0831

CPC classification number: G06F12/0815 ,  G06F12/0831 ,  G06F2212/1032

Abstract: A scalable cache coherency protocol for system including a plurality of coherent agents coupled to one or more memory controllers is described. The memory controller may implement a precise directory for cache blocks from the memory to which the memory controller is coupled. Multiple requests to a cache block may be outstanding, and snoops and completions for requests may include an expected cache state at the receiving agent, as indicated by a directory in the memory controller when the request was processed, to allow the receiving agent to detect race conditions. In an embodiment, the cache states may include a primary shared and a secondary shared state. The primary shared state may apply to a coherent agent that bears responsibility for transmitting a copy of the cache block to a requesting agent. In an embodiment, at least two types of snoops may be supported: snoop forward and snoop back.

公开(公告)号：US20230083397A1

公开(公告)日：2023-03-16

申请号：US18058105

申请日：2022-11-22

Applicant: Apple Inc.

Inventor： James Vash ,  Gaurav Garg ,  Brian P. Lilly ,  Ramesh B. Gunna ,  Steven R. Hutsell ,  Lital Levy-Rubin ,  Per H. Hammarlund ,  Harshavardhan Kaushikkar

IPC: G06F12/0815 ,  G06F12/0831

Abstract: A scalable cache coherency protocol for system including a plurality of coherent agents coupled to one or more memory controllers is described. The memory controller may implement a precise directory for cache blocks from the memory to which the memory controller is coupled. Multiple requests to a cache block may be outstanding, and snoops and completions for requests may include an expected cache state at the receiving agent, as indicated by a directory in the memory controller when the request was processed, to allow the receiving agent to detect race conditions. In an embodiment, the cache states may include a primary shared and a secondary shared state. The primary shared state may apply to a coherent agent that bears responsibility for transmitting a copy of the cache block to a requesting agent. In an embodiment, at least two types of snoops may be supported: snoop forward and snoop back.