公开(公告)号：US09891853B1

公开(公告)日：2018-02-13

申请号：US15000626

申请日：2016-01-19

Applicant: Apple Inc.

Inventor： Neeraj Parik ,  Gurjeet S. Saund ,  Rakesh L. Notani ,  Robert E. Jeter

IPC: G06F3/06 ,  G11C7/22 ,  G06F13/16

CPC classification number: G06F3/0629 ,  G06F3/0604 ,  G06F3/0673 ,  G06F13/1689 ,  G11C7/222 ,  G11C2207/2254

Abstract: A method and apparatus for selective calibrations of a memory subsystem is disclosed. The memory subsystem includes a memory and a memory controller. The memory controller is configured to periodically perform calibrations of a data strobe signal conveyed to the memory and a reference voltage used to distinguish between a logic 0 and a logic 1. The memory subsystem is also coupled to receive a clock signal (e.g., at the memory controller). If a pending change of frequency of the clock signal is indicated to the memory controller during performance of a periodic calibration, the reference voltage calibration may be aborted prior to or during the performance thereof, while the data strobe calibration may be completed.

公开(公告)号：US09691470B1

公开(公告)日：2017-06-27

申请号：US15188928

申请日：2016-06-21

Applicant: Apple Inc.

Inventor： Robert E. Jeter ,  Rakesh L. Notani

IPC: G11C7/06 ,  G11C11/4076 ,  G11C11/4074 ,  G11C11/4096

CPC classification number: G06F13/1689 ,  G11C29/023 ,  G11C29/028 ,  G11C29/50012

Abstract: An apparatus and method for a restricted range calibration is disclosed. A system includes a memory coupled to a memory controller. The memory controller is coupled to receive a clock signal, and is configured to operate in different performance states corresponding to different frequencies of the clock signal. The memory controller provides a data strobe signal to synchronize transfers of data to and from the memory. When operating in a first performance state, the memory controller may perform a first calibration of a delay applied to the data strobe signal. Performing the first calibration includes varying the delay over a first range of values. Thereafter, responsive to returning to the first performance state from another performance state, the memory controller may perform a second calibration. The second calibration includes varying the delay over a second range of values that is less than the first range.

公开(公告)号：US09672882B1

公开(公告)日：2017-06-06

申请号：US15083909

申请日：2016-03-29

Applicant: Apple Inc.

Inventor： Robert E. Jeter ,  Rakesh L. Notani

IPC: G11C7/22 ,  G11C29/04

CPC classification number: G11C7/1093 ,  G11C7/1066 ,  G11C2207/2254

Abstract: A method and apparatus for memory subsystem calibration in which periodic calibrations of a data strobe delay and reference voltage are scheduled. After a first calibration, a reference score is determined based on a parameter of an eye opening. On a next scheduled calibration thereafter, the data strobe delay is calibrated at the most recent value of the reference voltage. A score is then determined, and compared to the reference score. If the score is within a specified range of the reference score, then no calibration of the reference voltage is performed on the current cycle. Otherwise, the reference voltage is calibrated as well.

公开(公告)号：US09396778B1

公开(公告)日：2016-07-19

申请号：US14820815

申请日：2015-08-07

Applicant: Apple Inc.

Inventor： Robert E. Jeter ,  Kai Lun Hsiung ,  Rakesh L. Notani

IPC: G11C7/06 ,  G11C7/22 ,  G11C7/00 ,  G11C7/10

CPC classification number: G11C7/1009 ,  G06F13/1689 ,  G11C7/00 ,  G11C7/04 ,  G11C7/1066 ,  G11C7/1093 ,  G11C7/222 ,  G11C29/023 ,  G11C29/028 ,  G11C2207/2254

Abstract: A method and apparatus for conditional cancellation of a calibration procedure is performed. In one embodiment, a memory controller is coupled to memory. The memory controller is configured to convey data and a data strobe signal to the memory. The memory controller may conduct calibrations of a delay of the data strobe signal to ensure sufficient setup and hold time for the data. After an initial calibration, and at each of a number of periodic intervals, the memory controller may determine whether one or more parameters is within a specified range. If one of the one or more parameters is not within its respective specified range, another calibration of the data strobe delay may be performed. However, if each of the one or more parameters is within its respective specified range, the calibration may be canceled.

Abstract translation: 执行用于校准过程的条件消除的方法和装置。 在一个实施例中，存储器控制器耦合到存储器。 存储器控制器被配置为将数据和数据选通信号传送到存储器。 存储器控制器可以进行数据选通信号的延迟的校准，以确保数据的足够的建立和保持时间。 在初始校准之后，并且在多个周期性间隔的每一个周期，存储器控制器可以确定一个或多个参数是否在指定范围内。 如果一个或多个参数中的一个不在其相应的指定范围内，则可执行数据选通延迟的另一校准。 然而，如果一个或多个参数中的每一个在其各自的指定范围内，则可以取消校准。

公开(公告)号：US20220189519A1

公开(公告)日：2022-06-16

申请号：US17646741

申请日：2022-01-03

Applicant: Apple Inc.

Inventor： Robert E. Jeter ,  Rakesh L. Notani ,  Kai Lun Hsiung ,  Venkata Ramana Malladi ,  Rahul Ranjan ,  Naveen Kumar Korada

IPC: G11C7/22 ,  G06F11/10 ,  G11C7/10

Abstract: A memory subsystem and method for performing calibrations therein is disclosed. A memory subsystem includes a memory controller coupled to a memory by a plurality of signal paths. The memory controller is configured to perform an initial calibration to determine respective eye patterns corresponding to the ones of the plurality of signal paths. For a subsequent calibrations, updated eye patterns are determined for a subset of the plurality of signal paths. Remaining ones of the plurality of signal paths (not included in the subset), are not active during the subsequent calibrations. Updated eye patterns for the remaining ones of the plurality of signal paths are determined based on information obtained during the initial calibration and information from signal paths in the subset designated proxies for the remaining ones of the plurality of signal paths.

公开(公告)号：US11221798B2

公开(公告)日：2022-01-11

申请号：US16751975

申请日：2020-01-24

Applicant: Apple Inc.

Inventor： Gregory S. Mathews ,  Kai Lun Hsiung ,  Lakshmi Narasimha Murthy Nukala ,  Peter Fu ,  Rakesh L. Notani ,  Sukalpa Biswas ,  Thejasvi Magudilu Vijayaraj ,  Yanzhe Liu ,  Shane J. Keil

IPC: G06F3/06

Abstract: Techniques relating to arbitration in a memory controller are disclosed. In some embodiments, the memory controller is configured to transition between read turns and writes turn according to a turn schedule. In some embodiments, the memory controller also receives reports from circuitry requesting memory transactions and determines a current latency tolerance value based on the reports. In some embodiments, the memory controller is configured to switch from a write turn to a read turn prior to a scheduled switch based on the current latency tolerance meeting a threshold value.

公开(公告)号：US10991403B2

公开(公告)日：2021-04-27

申请号：US16277804

申请日：2019-02-15

Applicant: Apple Inc.

Inventor： Robert E. Jeter ,  Rakesh L. Notani ,  Venkata R. Malladi

IPC: G11C7/22

Abstract: A method and apparatus for performing memory calibration with endpoint replay is disclosed. A first calibration of a data strobe signal in a memory subsystem is performed. The first calibration includes determining initial values of first and second endpoints indicative of first and second delay values, respectively, applied to the data strobe signal. A second calibration of the data strobe signal is performed around these endpoints, within a range thereof that is less than a full range there between. Based on the second calibration, the endpoints are adjusted.

公开(公告)号：US20200266810A1

公开(公告)日：2020-08-20

申请号：US16277263

申请日：2019-02-15

Applicant: Apple Inc.

Inventor： Robert E. Jeter ,  Rakesh L. Notani ,  Kai Lun Hsiung ,  Yanzhe Liu

IPC: H03K5/156 ,  H03K3/017 ,  G11C11/409

Abstract: A method and apparatus for performing duty cycle correction with read/write calibrations is disclosed. A first calibration is performed in a memory subsystem having a memory and a memory controller. The first calibration includes conveying a first clock signal from the memory controller to the memory, and determining the duty cycle of the first clock signal. If the duty cycle is not within a specified range, the duty cycle is adjusted and the process repeated. After the duty cycle of the first clock signal is within the specified range, a second calibration is performed, the second calibration including conveying a second clock signal from the memory to the memory controller. The duty cycle of the first clock signal may be further adjusted based on the second calibration.

公开(公告)号：US10402121B2

公开(公告)日：2019-09-03

申请号：US15849945

申请日：2017-12-21

Applicant: Apple Inc.

Inventor： Rakesh L. Notani ,  Robert E. Jeter

IPC: G06F3/06

Abstract: A method and apparatus for performing performance state changes are disclosed. A power management circuit may be configured to receive requests for changes to first and second performance states for at least at least one memory of a plurality of memories. In response to a determination that a change to the first performance state is in progress, when the request to change to the second performance state is received, the power management controller may send a notification to a controller coupled to the memories. The controller may halt scheduling of memory interface calibration operations for the at least one memory based on the notification.

公开(公告)号：US09990973B1

公开(公告)日：2018-06-05

申请号：US15436212

申请日：2017-02-17

Applicant: Apple Inc.

Inventor： Robert E. Jeter ,  Rakesh L. Notani ,  Fabien S. Faure

IPC: G11C7/22

CPC classification number: G06F13/42 ,  G11C2207/2254

Abstract: A method and apparatus for using neighboring sampling points in a memory subsystem calibration is disclosed. In one embodiment, a memory subsystem includes a memory and a memory controller coupled thereto. A calibration unit in the memory controller is configured to perform calibrations of a data strobe signal and a reference voltage to determine eye openings for signals conveyed between the memory and the memory controller. Performing the calibration includes determining a number of different calibration points and computing initial scores for each of the calibration points. The method further includes calculating adjusted scores for each calibration point. For a given calibration point, the adjusted score includes weighted values of one or more calibration points that are adjacent thereto. The method further includes selecting a calibration point having the highest adjusted score as the calibrated value.