公开(公告)号：US20160350219A1

公开(公告)日：2016-12-01

申请号：US15133311

申请日：2016-04-20

Applicant: ARM LIMITED

Inventor： Andrew David TUNE ,  Sean James SALISBURY

IPC: G06F12/08

CPC classification number: G06F12/0817 ,  G06F12/0833 ,  G06F12/12 ,  G06F2212/1016

Abstract: A cache coherency controller comprises a directory indicating, for memory addresses cached by a group of two or more cache memories in a coherent cache structure, which of the cache memories are caching those memory addresses, the directory being associative so that multiple memory addresses map to an associative set of more than one directory entry; and control logic responsive to a memory address to be newly cached, and configured to detect whether one or more of the set of directory entries mapped to that memory address is available for storage of an indication of which of the two or more cache memories are caching that memory address; the control logic being configured so that when all of the set of directory entries mapped to that memory address are occupied, the control logic is configured to select one of the set of directory entries as a directory entry to be overwritten and the corresponding cached information to be invalidated, the control logic being configured to select a directory entry to be overwritten, from the set of directory entries, in dependence upon which of the group of two or more cache memories is indicated by that directory entry, according to a likelihood of selection amongst the two or more cache memories.

Abstract translation: 高速缓存一致性控制器包括一个目录，指示对于由相干高速缓存结构中的一组两个或多个高速缓存存储器缓存的存储器地址，哪个高速缓存存储器缓存那些存储器地址，该目录是关联的，使得多个存储器地址映射到 多个目录条目的关联集合; 以及响应于要高速缓存的存储器地址的控制逻辑，并且被配置为检测映射到该存储器地址的该组目录条目中的一个或多个是否可用于存储两个或多个高速缓存存储器中的哪一个缓存的指示 那个内存地址; 所述控制逻辑被配置为使得当映射到所述存储器地址的所有所述目录条目集合被占用时，所述控制逻辑被配置为将所述一组目录条目中的一个选择为要被覆盖的目录条目，并且将相应的缓存信息 根据选择的可能性，控制逻辑被配置为根据目录条目集合来选择要覆盖的目录条目，这取决于该目录条目指示两个或多个高速缓冲存储器的组中的哪一个 在两个或多个缓存存储器中。

公开(公告)号：US20160103776A1

公开(公告)日：2016-04-14

申请号：US14874801

申请日：2015-10-05

Applicant: ARM LIMITED

Inventor： Andrew David TUNE ,  Arthur Brian LAUGHTON ,  Daniel Adam SARA ,  Sean James SALISBURY ,  Peter Andrew RIOCREUX

IPC: G06F13/364 ,  G06F15/78 ,  G06F13/42

CPC classification number: G06F13/364 ,  G06F13/4282

Abstract: Interconnect circuitry 10 for connecting transaction masters 4, 6, 8 to transaction slaves 12, 14 includes response modification circuitry 18. The response modification circuitry includes shortlist buffer circuitry 28 storing identification for modification target transaction responses. The response modification circuitry 18 uses this identification data to identify among a stream of transaction responses in transit a modification target transaction response. The response modification circuitry 18 then serves to form a modified transaction response to be sent in place of the modification target transaction response to the transaction master 4, 6, 8.

Abstract translation: 用于将交易主机4,6,8连接到交易从站12,14的互连电路10包括响应修改电路18.响应修改电路包括存储用于修改目标事务响应的标识的候选列表缓冲器电路28。 响应修改电路18使用该识别数据来识别传送中的事务响应流中的修改目标事务响应。 响应修改电路18然后用于形成被修改的事务响应，以代替对交易主机4,6,8的修改目标事务响应。

公开(公告)号：US20150012719A1

公开(公告)日：2015-01-08

申请号：US13936749

申请日：2013-07-08

Applicant: ARM Limited

Inventor： Andrew David TUNE

IPC: G06F12/02

CPC classification number: G06F12/0223 ,  G06F12/0864 ,  G06F12/0891 ,  G06F12/0895 ,  Y02D10/13

Abstract: A data store has a data array for storing data values and a tag array for storing tag values for tracking which data values are stored in the data array. The associativity of the data array is greater than the associativity of the tag array. This means that fewer tag entries need to be accessed on each data access than in a conventional data store, reducing power consumption.

Abstract translation: 数据存储具有用于存储数据值的数据阵列和用于存储用于跟踪哪些数据值被存储在数据阵列中的标签值的标签阵列。 数据阵列的关联性大于标签数组的关联性。 这意味着在传统数据存储中，每个数据访问需要访问较少的标签条目，从而降低功耗。

公开(公告)号：US20140281180A1

公开(公告)日：2014-09-18

申请号：US13795680

申请日：2013-03-12

Applicant: ARM LIMITED

Inventor： Andrew David TUNE

IPC: G06F12/08

CPC classification number: G06F12/0817 ,  G06F12/0808 ,  G06F12/0831 ,  G06F12/0833 ,  G06F12/0864 ,  G06F12/0895

Abstract: A data processing system 3 employing a coherent memory system comprises multiple main cache memories 8. An inclusive snoop directory memory 14 stores directory lines 22. Each directory line includes a directory tag and multiple snoop vectors. Each snoop vector relates to a span of memory addresses corresponding to the cache line size within the main cache memories 8.

Abstract translation: 使用相干存储器系统的数据处理系统3包括多个主高速缓存存储器8.包含的窥探目录存储器14存储目录行22.每个目录行包括目录标签和多个侦听向量。 每个窥探向量涉及与主高速缓存存储器8内的高速缓存行大小相对应的存储器地址的跨度。

公开(公告)号：US20200026674A1

公开(公告)日：2020-01-23

申请号：US16037117

申请日：2018-07-17

Applicant: Arm Limited

Inventor： Andrew David TUNE

IPC: G06F13/366 ,  G06F9/50

Abstract: Arbitration circuitry is provided for allocating up to M resources to N requesters, where M≥2. The arbitration circuitry comprises group allocation circuitry to control a group allocation in which the N requesters are allocated to M groups of requesters, with each requester allocated to one of the groups; and M arbiters each corresponding to a respective one of the M groups. Each arbiter selects a winning requester from the corresponding group, which is to be allocated a corresponding resource of the M resources. In response to a given requester being selected as the winning requester by the arbiter for a given group, the group allocation is changed so that in a subsequent arbitration cycle the given requester is in a different group to the given group.

公开(公告)号：US20180189097A1

公开(公告)日：2018-07-05

申请号：US15396985

申请日：2017-01-03

Applicant: ARM Limited

Inventor： Alistair Crone BRUCE ,  Andrew David TUNE

IPC: G06F9/46 ,  G06F13/16 ,  G06F9/54

CPC classification number: G06F9/467 ,  G06F3/00 ,  G06F9/466 ,  G06F9/544 ,  G06F11/076 ,  G06F13/1663 ,  G06F13/1673

Abstract: Data processing apparatus comprises one or more transaction issuing devices configured to issue data processing transactions to be handled by a downstream device and to receive a completion acknowledgement in respect of each completed transaction; each transaction issuing device having associated transaction regulator circuitry configured to allow that transaction issuing device to issue transactions subject to a limit on a maximum number of outstanding transactions, an outstanding transaction being a transaction which has been issued but for which a completion acknowledgement has not yet been received; in which the downstream device is configured to issue an indication to a transaction issuing device, to authorise a change by the transaction regulator circuitry of the limit applicable to outstanding transactions by that transaction issuing device.

公开(公告)号：US20170315947A1

公开(公告)日：2017-11-02

申请号：US15139559

申请日：2016-04-27

Applicant: ARM Limited

Inventor： Ian David ANDREWS ,  Andrew David TUNE ,  Daniel Adam SARA ,  George Robert Scott LLOYD

IPC: G06F13/40 ,  G06F13/16 ,  G06F13/42

CPC classification number: G06F13/4022 ,  G06F13/1642 ,  G06F13/1673 ,  G06F13/4282 ,  Y02D10/14 ,  Y02D10/151

Abstract: A crossbar switch comprises two or more data inputs 10, two or more data outputs 100, a buffer 30 between the inputs and the outputs, an arbiter 52 associated with each output and configured to select data from one of the inputs when there is contention at the output, a bypass 32 associated with the buffer so that the buffer can be enabled or disabled, and a buffer controller 60 configured to enable or disable the buffer. The buffer controller further includes an accumulator 70 configured to assess whether a time-based average of the contention rate, or an average injection rate, at the output associated with the buffer, has reached a predetermined threshold. This prevents the buffer being enabled when the contention is only intermittent, which reduces power consumption without significant loss of performance.

公开(公告)号：US20160350220A1

公开(公告)日：2016-12-01

申请号：US15133341

申请日：2016-04-20

Applicant: ARM LIMITED

Inventor： Sean James SALISBURY ,  Andrew David TUNE

IPC: G06F12/08

CPC classification number: G06F12/0817 ,  G06F12/0813 ,  G06F2212/1016

Abstract: A cache coherency controller comprises a directory indicating, for memory addresses cached by one or more of a group of one or more cache memories connectable in a coherent cache structure, which of the cache memories are caching those memory addresses; and control circuitry configured to detect a directory entry relating to a memory address to be accessed so as to coordinate, amongst the cache memories, an access to a memory address by one of the cache memories or a coherent agent in instances when the directory entry indicates that another of the cache memories is caching that memory address; the control circuitry being responsive to status data indicating whether each cache memory in the group is currently subject to cache coherency control so as to take into account, in the detection of the directory entry relating to the memory address to be accessed, only those cache memories in the group which are currently subject to cache coherency control.

Abstract translation: 高速缓存一致性控制器包括一个目录，指示对于在一个连续高速缓存结构中可连接的一个或多个高速缓存存储器中的一个或多个存储器缓存的存储器地址，哪个高速缓存存储器缓存那些存储器地址; 以及控制电路，被配置为检测与要访问的存储器地址相关的目录条目，以便在所述高速缓冲存储器中，当所述目录条目指示的情况下，通过所述高速缓冲存储器之一或协调代理来协调对存储器地址的访问 另一个缓存存储器缓存该存储器地址; 控制电路响应状态数据，指示该组中的每个高速缓冲存储器当前是否经历高速缓存一致性控制，以便在检测与要访问的存储器地址相关的目录条目时仅考虑那些缓存存储器 在目前正在进行高速缓存一致性控制的组中。

公开(公告)号：US20160203094A1

公开(公告)日：2016-07-14

申请号：US14944340

申请日：2015-11-18

Applicant: ARM LIMITED

Inventor： Andrew David TUNE ,  Sean James SALISBURY

IPC: G06F13/40 ,  G06F13/42 ,  G06F13/16 ,  G06F12/08

CPC classification number: G06F13/4022 ,  G06F12/0815 ,  G06F12/0831 ,  G06F13/1673 ,  G06F13/4282 ,  G06F2212/1016 ,  G06F2212/622

Abstract: There is provided an interconnect for transferring requests between ports in which the ports include both source ports destination ports. The interconnect includes storage circuitry for storing the requests. Input circuitry receives the requests from the plurality of source ports, selects at least one selected source port from an allowed set of said plurality of source ports, and transfers a presented request from the at least one selected source port to the storage circuitry. Output circuitry causes a request in said storage circuitry to be output at one of said plurality of destination ports. Counter circuitry maintains counter values for a plurality of tracked ports from amongst said ports, each counter value indicating the number of requests in said storage circuitry associated with a corresponding tracked port that are waiting to be output by said output circuitry and filter circuitry determines whether or not a given source port is in said allowed set in dependence on said counter circuitry.

Abstract translation: 提供了用于在端口之间传送请求的互连，其中端口包括源端口目的端口。 互连包括用于存储请求的存储电路。 输入电路接收来自多个源端口的请求，从所述多个源端口的允许集合中选择至少一个选择的源端口，并将所呈现的请求从所述至少一个选择的源端口传送到存储电路。 输出电路使所述存储电路中的请求在所述多个目的地端口之一处输出。 计数器电路维护来自所述端口中的多个跟踪端口的计数器值，每个计数器值指示与正在等待由所述输出电路输出的相应跟踪端口相关联的所述存储电路中的请求数，并且滤波器电路确定是否 根据所述计数器电路，给定的源端口不在所述允许的集合中。

公开(公告)号：US20160062893A1

公开(公告)日：2016-03-03

申请号：US14822953

申请日：2015-08-11

Applicant: ARM LIMITED

Inventor： Andrew David TUNE ,  Sean James SALISBURY

IPC: G06F12/08

CPC classification number: G06F12/0833 ,  G06F12/0808 ,  G06F12/0831 ,  G06F2212/62 ,  G06F2212/621 ,  Y02D10/13

Abstract: An interconnect and method of managing a snoop filter within such an interconnect are provided. The interconnect is used to connect a plurality of devices, including a plurality of master devices where one or more of the master devices has an associated cache storage. The interconnect comprises coherency control circuitry to perform coherency control operations for data access transactions received by the interconnect from the master devices. In performing those operations, the coherency control circuitry has access to snoop filter circuitry that maintains address-dependent caching indication data, and is responsive to a data access transaction specifying a target address to produce snoop control data providing an indication of which master devices have cached data for the target address in their associated cache storage. The coherency control circuitry then responds to the snoop control data by issuing a snoop transaction to each master device indicated by the snoop control data, in order to cause a snoop operation to be performed in their associated cache storage in order to generate snoop response data. Analysis circuitry then determines from the snoop response data an update condition, and upon detection of the update condition triggers performance of an update operation within the snoop filter circuitry to update the address-dependent caching indication data. By subjecting the snoop response data to such an analysis, it is possible to identify situations where the caching indication data has become out of date, and update that caching indication data accordingly, this giving rise to significant performance benefits in the operation of the interconnect.

Abstract translation: 提供了在这种互连内管理窥探滤波器的互连和方法。 互连用于连接多个设备，包括多个主设备，其中一个或多个主设备具有相关联的高速缓存存储器。 互连包括一致性控制电路，用于对由主设备的互连接收的数据访问事务执行一致性控制操作。 在执行这些操作时，相关性控制电路可以访问保持地址相关的缓存指示数据的窥探滤波器电路，并且响应于指定目标地址的数据访问事务来产生窥探控制数据，提供哪些主设备已被缓存的指示 其相关缓存存储中的目标地址的数据。 相关性控制电路然后通过向窥探控制数据指示的每个主设备发出窥探事务来响应窥探控制数据，以便在其关联的高速缓存存储器中执行窥探操作，以便产生窥探响应数据。 分析电路然后从窥探响应数据确定更新条件，并且在检测到更新条件时，触发窥探过滤器电路内的更新操作的执行，以更新依赖于地址的高速缓存指示数据。 通过对窥探响应数据进行这种分析，可以识别高速缓存指示数据已经过时的情况，并相应地更新缓存指示数据，这在互连操作中产生显着的性能益处。