公开(公告)号：US11144458B2

公开(公告)日：2021-10-12

申请号：US15549284

申请日：2016-01-12

Applicant: ARM LIMITED

Inventor： Jason Parker ,  Bruce James Mathewson ,  Matthew Lucien Evans

IPC: G06F12/00 ,  G06F12/0831 ,  G06F12/1009 ,  G06F12/10

Abstract: An apparatus (2) comprises processing circuitry (4) for performing data processing in response to instructions. The processing circuitry (4) supports a cache maintenance instruction (50) specifying a virtual page address (52) identifying a virtual page of a virtual address space. In response to the cache maintenance instruction, the processing circuitry (4) triggers at least one cache (18, 20, 22) to perform a cache maintenance operation on one or more cache lines for which a physical address of the data stored by the cache line is within a physical page that corresponds to the virtual page identified by the virtual page address provided by the cache maintenance instruction.

公开(公告)号：US10579526B2

公开(公告)日：2020-03-03

申请号：US15427410

申请日：2017-02-08

Applicant: ARM Limited

Inventor： Phanindra Kumar Mannava ,  Bruce James Mathewson ,  Jamshed Jalal ,  Klas Magnus Bruce

IPC: G06F12/08 ,  G06F12/0831 ,  G06F13/16

Abstract: A data processing apparatus includes receiving circuitry to receive a snoop request sent by a source node in respect of requested data and transmitting circuitry. Cache circuitry caches at least one data value. The snoop request includes an indication as to whether the requested data is to be returned to the source node and when the at least one data value includes the requested data, the transmitting circuitry transmits a response to the source node including said requested data, in dependence on said indication.

公开(公告)号：US10185663B2

公开(公告)日：2019-01-22

申请号：US15427409

申请日：2017-02-08

Applicant: ARM Limited

Inventor： Jamshed Jalal ,  Michael Filippo ,  Bruce James Mathewson ,  Phanindra Kumar Mannava

IPC: G06F12/08 ,  G06F12/0888 ,  G06F12/0811 ,  G06F12/0862 ,  G06F12/0831 ,  G06F12/128

Abstract: A data processing apparatus is provided including a memory hierarchy having a plurality of cache levels including a forwarding cache level, at least one bypassed cache level, and a receiver cache level. The forwarding cache level forwards a data access request relating to a given data value to the receiver cache level, inhibiting the at least one bypassed cache level from responding to the data access request. The receiver cache level includes presence determination circuitry for performing a determination as to whether the given data value is present in the at least one bypassed cache level. In response to the determination indicating that the data value is present in the at least one bypassed cache level, one of the at least one bypassed cache level is made to respond to the data access request.

公开(公告)号：US11537543B2

公开(公告)日：2022-12-27

申请号：US17189781

申请日：2021-03-02

Applicant: Arm Limited

Inventor： Ashok Kumar Tummala ,  Jamshed Jalal ,  Antony John Harris ,  Jeffrey Carl Defilippi ,  Anitha Kona ,  Bruce James Mathewson

IPC: G06F13/38 ,  G06F13/40

Abstract: An apparatus and method are provided for handling protocol conversion. The apparatus has interconnect circuitry for routing messages between components coupled to the interconnect circuitry in a manner that conforms to a first communication protocol. Protocol conversion circuitry is coupled between the interconnect circuitry and an external communication path, for converting messages between the first communication protocol and a second communication protocol that has a layered architecture comprising multiple layers. The protocol conversion circuitry has a gateway component forming one of the components coupled to the interconnect circuitry, and a controller coupled with the gateway component and used to control connection with the external communication path. For a selected layer of the multiple layers, the protocol conversion circuitry provides, within the gateway component, upper selected layer circuitry to implement a first portion of functionality of the selected layer, where the first portion comprises at least protocol dependent functionality of the selected layer. It also provides, within the controller, lower selected layer circuitry to implement a remaining portion of the functionality of the selected layer, the remaining portion comprising only protocol independent functionality of the selected layer.

公开(公告)号：US11269773B2

公开(公告)日：2022-03-08

申请号：US16595863

申请日：2019-10-08

Applicant: Arm Limited

Inventor： Bruce James Mathewson ,  Phanindra Kumar Mannava ,  Jamshed Jalal ,  Klas Magnus Bruce ,  Andrew John Turner

IPC: G06F9/52 ,  G06F9/30 ,  G06F15/78 ,  G06F13/42 ,  G06F13/16 ,  G06F12/0831 ,  G06F12/0817 ,  G06F12/0815

Abstract: Circuitry comprises a set of two or more data handling nodes each having respective storage circuitry to hold data; and a home node to serialise data access operations and to control coherency amongst data held by the one or more data handling nodes so that data written to a memory address is consistent with data read from that memory address in response to a subsequent access request; in which: a requesting node of the set of data handling nodes is configured to communicate a request to the home node for exclusive access to a given instance of data at a given memory address; and the home node is configured, in response to the request, to communicate information to other data handling nodes of the set of data handling nodes to control handling, by those other data handling nodes, of any further instances of the data at the given memory address which are held by those other data handling nodes.

公开(公告)号：US10949292B1

公开(公告)日：2021-03-16

申请号：US16594223

申请日：2019-10-07

Applicant: Arm Limited

Inventor： Bruce James Mathewson ,  Phanindra Kumar Mannava ,  Michael Andrew Campbell ,  Alexander Alfred Hornung ,  Alex James Waugh ,  Klas Magnus Bruce ,  Richard Roy Grisenthwaite

IPC: G06F11/20 ,  G11C29/08 ,  G06F11/10 ,  G11C29/18 ,  G06F11/30

Abstract: A requester issues a request specifying a target address indicating an addressed location in a memory system. A completer responds to the request. Tag error checking circuitry performs a tag error checking operation when the request issued by the requester is a tag-error-checking request specifying an address tag. The tag error checking operation comprises determining whether the address tag matches an allocation tag stored in the memory system associated with a block of one or more addresses comprising the target address specified by the tag-error-checking request. The requester and the completer communicate via a memory interface having at least one data signal path to exchange read data or write data between the requester and the completer; and at least one tag signal path, provided in parallel with the at least one data signal path, to exchange address tags or allocation tags between the requester and the completer.

公开(公告)号：US10917198B2

公开(公告)日：2021-02-09

申请号：US16027864

申请日：2018-07-05

Applicant: Arm Limited

Inventor： Phanindra Kumar Mannava ,  Bruce James Mathewson ,  Jamshed Jalal ,  Tushar P. Ringe

IPC: H04L29/08 ,  H04L1/16

Abstract: In a data processing network comprising one or more Request Nodes and a Home Node coupled via a coherent interconnect, a Request Node requests data from the Home Node. The requested data is sent, via the interconnect, to the Request Node in a plurality of data beats, where a first data beat of the plurality of data beats is received at a first time and a last data beat is received at a second time. Responsive to receiving the first data beat, the Request Node sends an acknowledgement message to the Home Node. Upon receipt of the acknowledgement message, the Home Node frees resources allocated to the read transaction. In addition, the Home Node is configured to allow snoop requests for the data to the Request Node to be sent to the Request Node before all beats of the requested data have been received by the Request Node.

公开(公告)号：US10664399B2

公开(公告)日：2020-05-26

申请号：US15825633

申请日：2017-11-29

Applicant: ARM Limited

Inventor： Håkan Lars-Göran Persson ,  Ian Rudolf Bratt ,  Andrew Brookfield Swaine ,  Bruce James Mathewson

IPC: G06F12/0831 ,  G06F13/16

Abstract: A filter comprises interface circuitry, to intercept coherency protocol transactions exchanged between a master device comprising a first cache and an interconnect for managing coherency between the first cache and at least one other cache or other master device. The filter has filtering circuitry for filtering the coherency protocol transactions in dependence on memory access permission data defining which regions of an address space the master device is allowed to access.

公开(公告)号：US10282297B2

公开(公告)日：2019-05-07

申请号：US15427320

申请日：2017-02-08

Applicant: ARM Limited

Inventor： Phanindra Kumar Mannava ,  Bruce James Mathewson ,  Jamshed Jalal ,  Mark David Werkheiser

IPC: G06F12/08 ,  G06F12/0831 ,  G06F12/0804 ,  G06F12/0808 ,  G06F12/0811 ,  G06F12/084 ,  G06F12/0842 ,  G06F12/0891 ,  G06F12/0897

Abstract: A system comprises a number of master devices and an interconnect for managing coherency between the master devices. In response to a read-with-overridable-invalidate transaction received by the interconnect from a requesting master device requesting that target data associated with a target address is provided to the requesting master device, when target data associated with the target address is stored by a cache, the interconnect issues a snoop request to said cache triggering invalidation of the target data from the cache except when the interconnect or cache determines to override the invalidation and retain the target data in the cache. This enables greater efficiency in cache usage since data which the requesting master considers is unlikely to be needed again can be invalidated from caches located outside the master device itself.

公开(公告)号：US09830294B2

公开(公告)日：2017-11-28

申请号：US14579316

申请日：2014-12-22

Applicant: ARM Limited

Inventor： Bruce James Mathewson ,  Daren Croxford ,  Jason Parker

IPC: G06F13/00 ,  G06F13/40 ,  G06F13/364 ,  G06F13/42 ,  G06F12/0831

CPC classification number: G06F13/4068 ,  G06F12/0831 ,  G06F13/364 ,  G06F13/4022 ,  G06F13/4221 ,  G06F2212/1016 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D10/151

Abstract: A data processing system having a master device and a plurality of slave devices uses interconnect circuitry to couple the master device with the plurality of slave devices to enable transactions to be performed by the slave devices upon request from the master device. The master device issues a multi-transaction request identifying multiple transactions to be performed, the multi-transaction request providing a base transaction identifier, a quantity indication indicating a number of transactions to be performed, and address information. Request distribution circuitry within the interconnect circuitry analyses the address information and the quantity indication in order to determine, for each of the multiple transactions, the slave device that is required to perform that transaction. Transaction requests are then issued from the request distribution circuitry to each determined slave device to identify which transactions need to be performed by each slave device. Each determined slave device provides a response to the master device to identify completion of each transaction performed by that determined slave device. Each determined slave device provides its responses independently of the responses from any other determined slave device, and each response includes a transaction identifier determined from the base transaction identifier and transaction specific information. This enables the master device to identify completion of each transaction identified within the multi-transaction request. In an alternative arrangement, the same multi-transaction request approach can be used by a master device to initiate cache maintenance operations within a plurality of cache storage devices. This approach can give rise to significant improvements in efficiency and power consumption within the data processing system.