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21.发明授权Array substrate, manufacturing method for the same, display device and electronic product 有权阵列基板，制造方法相同，显示装置和电子产品公开(公告)号：US09461078B1
公开(公告)日：2016-10-04
申请号：US14414713
申请日：2014-04-08
发明人： Jinchao Bai , Yao Liu , Liangliang Li , Xiangqian Ding , Zongjie Guo
IPC分类号： H01L23/48 , H01L27/12 , H01L21/768 , H01L21/027 , H01L21/311 , G02F1/1368 , G02F1/1343 , G02F1/1333 , G02F1/1362
CPC分类号： H01L27/1288 , G02F1/133345 , G02F1/134309 , G02F1/134363 , G02F1/1345 , G02F1/1362 , G02F1/136227 , G02F1/136286 , G02F1/1368 , G02F2001/134372 , G02F2001/136231 , G02F2001/136236 , G02F2001/13629 , G02F2001/136295 , H01L21/0274 , H01L21/31144 , H01L21/76802 , H01L21/76877 , H01L27/124
摘要： According to the method for manufacturing an array substrate of the present disclosure, when two non-adjacent conductive layers are electrically connected to each other through the via-holes, the insulating layers between the adjacent conductive layers may be etched by several etching processes so as to form the corresponding via-holes in the insulating layer, thereby to achieve the electrical connection between the non-adjacent conductive layers. Meanwhile, it is also able to achieve the electrical connection between the adjacent conductive layers through the via-holes in each etching process. In other words, when at least three conductive layers are electrically connected with each other through the via-holes, merely the insulating layer between the adjacent conductive layers is etched in each etching process.
摘要翻译： 根据本公开的阵列基板的制造方法，当两个不相邻的导电层通过通孔彼此电连接时，相邻导电层之间的绝缘层可以通过若干蚀刻工艺进行蚀刻，以便 以在绝缘层中形成对应的通孔，从而实现非相邻导电层之间的电连接。 同时，也可以在每个蚀刻工艺中通过通孔实现相邻导电层之间的电连接。 换句话说，当至少三个导电层通过通孔彼此电连接时，在每个蚀刻工艺中仅蚀刻相邻导电层之间的绝缘层。
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公开(公告)号：US09412761B2
公开(公告)日：2016-08-09
申请号：US14794240
申请日：2015-07-08
发明人： Jinchao Bai , Yao Liu , Liangliang Li , Zhaohui Hao , Liang Sun
IPC分类号： H01L29/04 , H01L29/10 , H01L31/00 , H01L27/12 , G02F1/1362 , G02F1/1345 , G02F1/1368 , G02F1/1343
CPC分类号： H01L27/124 , G02F1/133345 , G02F1/1345 , G02F1/136227 , G02F1/136286 , G02F1/1368 , G02F2001/134318 , G02F2201/121 , G02F2201/123 , G02F2201/40 , H01L23/3171 , H01L27/1214 , H01L27/1218 , H01L27/1248
摘要： An array substrate, a method for manufacturing the same and a display apparatus are provided. The array substrate comprises: a substrate (1); a common electrode (2) and a pixel electrode (10) sequentially formed on the substrate (1) and insulated from each other; a thin film transistor comprising a gate electrode (4), an active layer (7), a source electrode (8a) and a drain electrode (8b), wherein the drain electrode (8b) is electrically connected with the pixel electrode (10); a common electrode line (5) disposed in a same layer as the gate electrode (4); and an insulating layer (3) between the gate electrode (4) and the common electrode (2), wherein the common electrode (2) is connected with the common electrode line (5) through a through hole in the insulating layer (3).
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公开(公告)号：US09378953B2
公开(公告)日：2016-06-28
申请号：US14526777
申请日：2014-10-29
发明人： Liangliang Li , Zongjie Guo , Huibin Guo , Shoukun Wang , Yuchun Feng , Xiaowei Liu
CPC分类号： H01L21/02691 , C04B41/0036 , C04B41/0072 , C04B41/5353 , C04B41/91 , H01L21/02422 , H01L21/02554 , H01L21/02565 , H01L21/02631 , H01L21/02686
摘要： Disclosed is a method for preparing a polycrystalline metal oxide pattern, characterized by comprising: annealing a predetermined region of an amorphous metal oxide film by laser, so as to convert the amorphous metal oxide in the predetermined region into a polycrystalline metal oxide; and etching the amorphous metal oxide outside of the predetermined region so as to remove it. By the method according to the present invention, firstly, the predetermined region of an amorphous metal oxide film is annealed by laser so as to convert the amorphous metal oxide into a polycrystalline metal oxide, and then, the amorphous metal oxide outside of the predetermined region is etched away, thereby a polycrystalline metal oxide pattern is formed. The method for preparing a polycrystalline metal oxide pattern according to the present invention is simple, and can effectively shorten the production period and save production costs.
摘要翻译： 公开了一种制备多晶金属氧化物图案的方法，其特征在于包括：通过激光对预定区域的非晶金属氧化物膜进行退火，以将预定区域中的非晶态金属氧化物转化为多晶金属氧化物; 并且在预定区域外蚀刻非晶态金属氧化物以便将其去除。 根据本发明的方法，首先，通过激光对非晶金属氧化物膜的预定区域进行退火，以将非晶金属氧化物转化为多晶金属氧化物，然后在预定区域外部的非晶态金属氧化物 被蚀刻掉，从而形成多晶金属氧化物图案。 根据本发明的多晶金属氧化物图案的制备方法简单，可以有效缩短生产周期，节省生产成本。
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公开(公告)号：US20150367286A1
公开(公告)日：2015-12-24
申请号：US14521400
申请日：2014-10-22
发明人： Liangliang Li , Zongjie Guo , Xiangqian Ding , Yao Liu , Jinchao Bai
摘要： The embodiments of the present disclosure provide an etching liquid storage apparatus and a wet etching device, which relates to the field of display technology, and can reduce the concentration of foreign ions in the etching liquid, so as to avoid frequent replacement of the etching liquid, thereby ensuring stability of the etching process, meanwhile, can also prolong the service life of the etching liquid, so as to reduce the cost; the etching liquid storage apparatus comprises an etching liquid storage tank, an ion exchange membrane for enabling selective permeation of ions in the etching liquid, and an anode or a cathode located at both sides of the ion exchange membrane; wherein a first chamber is formed between the ion exchange membrane and the anode, a second chamber is formed between the ion exchange membrane and the cathode; it is used for manufacture of the wet etching device.
摘要翻译： 本公开的实施例提供了一种与显示技术领域相关的蚀刻液体存储装置和湿式蚀刻装置，并且可以减少蚀刻液中的外来离子的浓度，以避免频繁地更换蚀刻液 从而确保了蚀刻工艺的稳定性，同时也可以延长蚀刻液的使用寿命，降低成本; 蚀刻液体储存装置包括蚀刻液体储存罐，用于使蚀刻液体中的离子能够选择性渗透的离子交换膜和位于离子交换膜两侧的阳极或阴极; 其中在所述离子交换膜和所述阳极之间形成第一室，在所述离子交换膜和所述阴极之间形成第二室; 用于制造湿蚀刻装置。
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公开(公告)号：US10379413B2
公开(公告)日：2019-08-13
申请号：US15521339
申请日：2016-11-02
发明人： Shoukun Wang , Liangliang Li , Yuchun Feng , Huibin Guo
IPC分类号： G02F1/1362 , G02F1/1368 , H01L27/12
摘要： This present disclosure provides an array substrate, a manufacturing method thereof, and a display apparatus, aiming at solving the issue of light reflection on the array substrates and improving the display effects of display apparatuses. The array substrate includes a transparent substrate; a plurality of components disposed on a first side of the transparent substrate; and a shielding pattern, disposed on a second side of the transparent substrate, and configured to shield light reflected from a surface of at least one of the plurality of components.
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公开(公告)号：US10282005B2
公开(公告)日：2019-05-07
申请号：US15314161
申请日：2016-03-23
发明人： Liangliang Li , Huibin Guo , Tsung Chieh Kuo , Xi Chen , Yuchun Feng , Shoukun Wang , Jing Wang
摘要： A touch display panel, a manufacturing method thereof and a method of detecting a touch for the same are disclosed. The touch display panel includes a first substrate (01) and a second substrate (02). The first substrate (01) includes, within its non-display region, a plurality of gate lines (10) parallel to each other, a plurality of data lines (20) parallel to each other, a plurality of first touch electrode lines (30) parallel to the gate lines (10), and a plurality of second touch electrode lines (40) parallel to the data lines (20). The first substrate (01) further includes first touch electrodes (50) electrically connected to the first touch electrode lines (30) and second touch electrodes (60) electrically connected to the second touch electrode lines (40). Between two adjacent data lines (20), there are two sub-pixels arranged in the same row on the first substrate (01). A second touch electrode line (40) is located between the two sub-pixels. A pair of gate lines (10) are located between any two adjacent rows of sub-pixels on the first substrate (01), and a first touch electrode lines (30) is located between the pair of the gate lines (10). Since the first touch electrode line (30) and the second touch electrode line (40) are disposed within the light-proof non-display region, their impact on the aperture ratio can be avoided.
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公开(公告)号：US10014329B2
公开(公告)日：2018-07-03
申请号：US14436843
申请日：2014-09-11
发明人： Jinchao Bai , Xiangqian Ding , Yao Liu , Liangliang Li , Zongjie Guo
CPC分类号： H01L27/1248 , H01L27/124 , H01L27/127 , H01L27/1288
摘要： An array substrate and manufacturing method thereof and display device are provided. The method of manufacturing the array substrate includes forming a pattern including a gate electrode, a gate line, a common electrode line and a gate insulating layer on a substrate; forming a pattern including a data line, a source electrode, a drain electrode and an active layer; forming a pattern including an insulating interlayer over the pattern of the source electrode, the drain electrode and the active layer; forming a pattern including a first transparent electrode over the insulating interlayer; forming a pattern including a passivation layer over the first transparent electrode; and forming a pattern including a second transparent electrode over the passivation layer. The method can efficiently prevent the ITO process polluting the TFT channel.
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公开(公告)号：US20150277197A1
公开(公告)日：2015-10-01
申请号：US14316039
申请日：2014-06-26
发明人： Xi Chen , Guoqi Mao , Liangliang Li , Yao Liu
IPC分类号： G02F1/1362 , G02F1/1368
CPC分类号： G02F1/136259 , G02F2001/136263
摘要： An array substrate, a method for repairing the same and a display apparatus are disclosed. The array substrate, comprises: a plurality of first signal lines and a plurality of second signal lines; a plurality of pixel units each comprising a thin film transistor and a pixel electrode; and connecting assemblies comprising a plurality of first portions arranged in the layer in which the second signal lines are located and a plurality of second portions arranged in the layer in which the pixel electrodes are located, the first signal lines, the second signal lines and the pixel electrodes being in different layers on the array substrate respectively, the first portions and the second portions in the connecting assemblies being arranged alternatively, the plurality of first portions being partly overlapped with the first signal lines respectively, the second portions being partly overlapped with adjacent first portions.
摘要翻译： 公开了阵列基板，其修补方法和显示装置。 阵列基板包括：多条第一信号线和多条第二信号线; 多个像素单元，每个像素单元包括薄膜晶体管和像素电极; 以及连接组件，包括布置在第二信号线所在的层中的多个第一部分和布置在像素电极所在的层中的多个第二部分，第一信号线，第二信号线和 像素电极分别位于阵列基板上的不同层中，连接组件中的第一部分和第二部分交替布置，多个第一部分分别与第一信号线部分重叠，第二部分与相邻部分重叠 第一部分。
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29.发明授权公开(公告)号：US09146431B2
公开(公告)日：2015-09-29
申请号：US13976498
申请日：2012-11-12
发明人： Jinchao Bai , Yao Liu , Liangliang Li , Zhaohui Hao , Liang Sun
IPC分类号： H01L21/00 , G02F1/1345 , G02F1/1362 , H01L27/12 , G02F1/1368 , G02F1/1343
CPC分类号： H01L27/124 , G02F1/133345 , G02F1/1345 , G02F1/136227 , G02F1/136286 , G02F1/1368 , G02F2001/134318 , G02F2201/121 , G02F2201/123 , G02F2201/40 , H01L23/3171 , H01L27/1214 , H01L27/1218 , H01L27/1248
摘要： An array substrate, a method for manufacturing the same and a display apparatus are provided. The array substrate comprises: a substrate (1); a common electrode (2) and a pixel electrode (10) sequentially formed on the substrate (1) and insulated from each other; a thin film transistor comprising a gate electrode (4), an active layer (7), a source electrode (8a) and a drain electrode (8b), wherein the drain electrode (8b) is electrically connected with the pixel electrode (10); a common electrode line (5) disposed in a same layer as the gate electrode (4); and an insulating layer (3) between the gate electrode (4) and the common electrode (2), wherein the common electrode (2) is connected with the common electrode line (5) through a through hole in the insulating layer (3).
摘要翻译： 提供阵列基板，其制造方法和显示装置。 阵列基板包括：基板（1）; 依次形成在所述基板（1）上并且彼此绝缘的公共电极（2）和像素电极（10）; 包括栅极（4），有源层（7），源电极（8a）和漏电极（8b）的薄膜晶体管，其中漏电极（8b）与像素电极（10）电连接， ; 设置在与栅电极（4）相同的层中的公共电极线（5）; 以及在所述栅电极（4）和所述公共电极（2）之间的绝缘层（3），其中所述公共电极（2）通过所述绝缘层（3）中的通孔与所述公共电极线（5）连接， 。
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公开(公告)号：US08962404B2
公开(公告)日：2015-02-24
申请号：US14077770
申请日：2013-11-12
发明人： Jinchao Bai , Liang Sun , Xiangqian Ding , Liangliang Li , Yao Liu
CPC分类号： H01L27/1288 , H01L27/124 , H01L27/127 , H01L29/66765
摘要： A method for manufacturing fan-out lines on an array substrate is disclosed. The fan-out lines comprise an amorphous silicon layer, an ohmic contact layer and a source-drain electrode layer disposed on a gate insulating layer. The manufacturing processes can be conducted by forming a first layer of photoresist on the source-drain electrode layer and performing a half-exposure development process on the first layer of photoresist; etching the amorphous silicon layer, the ohmic contact layer and the source-drain electrode layer by an etching process; removing the first layer of photoresist; forming a second layer of photoresist and performing full-exposure development process on the second layer of photoresist; and etching the amorphous silicon layer by etching process to form the fan-out lines.
摘要翻译： 公开了一种在阵列基板上制造扇出线的方法。 扇出线包括非晶硅层，欧姆接触层和设置在栅极绝缘层上的源极 - 漏极电极层。 可以通过在源极 - 漏极电极层上形成第一层光致抗蚀剂并在第一层光致抗蚀剂上进行半曝光显影处理来进行制造工艺; 通过蚀刻工艺蚀刻非晶硅层，欧姆接触层和源极 - 漏极电极层; 去除第一层光刻胶; 形成第二层光致抗蚀剂并在第二层光致抗蚀剂上进行全曝光显影处理; 并通过蚀刻工艺蚀刻非晶硅层以形成扇出线。
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