公开(公告)号：US06410383B1

公开(公告)日：2002-06-25

申请号：US09527541

申请日：2000-03-16

Applicant: Yanjun Ma

Inventor： Yanjun Ma

IPC: H01L218242

CPC classification number: H01L21/76859 ,  H01L21/76843 ,  H01L21/76864

Abstract: A method of forming conducting diffusion barriers by depositing an initial film and implanting ions to modify the film is provided. An initial film having good step coverage is deposited over a semiconductor substrate. The initial material need not have the desired properties for a conducting diffusion barrier, but preferably contains one or more elements to be used in forming a desired film with the appropriate properties. The initial material is deposited by CVD, PECVD or IMP deposition. Ions are preferably implanted using plasma immersion ion implantation (PIII), although other methods are also provided. The method of the present invention produces binary, ternary, quaternary and other more complex films, while providing adequate step coverage.

Abstract translation: 提供了通过沉积初始膜并注入离子来修饰膜来形成导电扩散阻挡层的方法。 在半导体衬底上沉积具有良好阶梯覆盖率的初始膜。 初始材料不需要具有用于导电扩散阻挡层的所需性质，但优选包含一种或多种用于形成具有适当性质的所需膜的元素。 初始材料通过CVD，PECVD或IMP沉积沉积。 优选使用等离子体浸没离子注入（PIII）植入离子，尽管也提供了其它方法。 本发明的方法产生二元，三元，四元和其它更复杂的膜，同时提供足够的步骤覆盖。

公开(公告)号：US06406947B1

公开(公告)日：2002-06-18

申请号：US09740126

申请日：2000-12-18

Applicant: Yanjun Ma ,  Sheng Teng Hsu

Inventor： Yanjun Ma ,  Sheng Teng Hsu

IPC: H01L2100

CPC classification number: H01L29/66651 ,  H01L21/84 ,  H01L29/66772 ,  H01L29/783 ,  H01L29/7832 ,  H01L29/78612 ,  H01L29/78648

Abstract: A method of fabricating a dynamic threshold voltage metal oxide semiconductor (DTMOS) for operation at threshold voltages less than 0.6 volts includes preparing a silicon substrate to form a trench in an active area; forming a silicon layer in the trench; doping the silicon layer in the trench to form a highly doped layer, having a doping ion concentration in a range of between about 5.0·1017 cm−3 and 5.0·1018 cm−3; depositing a silicon layer over the high doped silicon layer; and completing the structure to form a DTMOS transistor.

Abstract translation: 制造用于在小于0.6伏特的阈值电压下操作的动态阈值电压金属氧化物半导体（DTMOS）的方法包括制备硅衬底以在有源区中形成沟槽; 在沟槽中形成硅层; 在沟槽中掺杂硅层以形成掺杂浓度在约5.0×10 17 cm -3至5.0×10 18 cm -3之间的掺杂离子浓度的高掺杂层; 在所述高掺杂硅层上沉积硅层; 并完成结构以形成DTMOS晶体管。

公开(公告)号：US06207589B1

公开(公告)日：2001-03-27

申请号：US09515743

申请日：2000-02-29

Applicant: Yanjun Ma ,  Yoshi Ono

Inventor： Yanjun Ma ,  Yoshi Ono

IPC: H01L2131

CPC classification number: H01L21/28185 ,  H01L21/28194 ,  H01L28/56 ,  H01L29/513 ,  H01L29/517

Abstract: A high-k dielectric film is provided which remains amorphous at relatively high annealing temperatures. The high-k dielectric film is a metal oxide of either Zr or Hf, doped with a trivalent metal, such as Al. Because the film resists the formation of a crystalline structure, interfaces to adjacent films have fewer irregularities. When used as a gate dielectric, the film can be made thin to support smaller transistor geometries, while the surface of the channel region can be made smooth to support high electron mobility. Also provided are CVD, sputtering, and evaporation deposition methods for the above-mentioned, trivalent metal doped high dielectric films.

Abstract translation: 提供了一种高k电介质膜，其在相对高的退火温度下保持非晶态。 高k电介质膜是掺杂有三价金属如Al的Zr或Hf的金属氧化物。 由于膜抵抗晶体结构的形成，与相邻膜的界面具有较少的不规则性。 当用作栅极电介质时，可以使膜变薄以支持更小的晶体管几何形状，同时沟道区域的表面可以被制成平滑的以支持高电子迁移率。 还提供了用于上述三价金属掺杂的高介电膜的CVD，溅射和蒸发沉积方法。

公开(公告)号：US06200866B1

公开(公告)日：2001-03-13

申请号：US09410346

申请日：1999-09-30

Applicant: Yanjun Ma ,  Douglas J. Tweet ,  David R. Evans ,  Yoshi Ono

Inventor： Yanjun Ma ,  Douglas J. Tweet ,  David R. Evans ,  Yoshi Ono

IPC: H01L21338

CPC classification number: H01L21/31053 ,  H01L21/2807 ,  H01L21/28194 ,  H01L21/28202 ,  H01L21/76801 ,  H01L21/76804 ,  H01L21/76834 ,  H01L29/41733 ,  H01L29/41775 ,  H01L29/41783 ,  H01L29/4908 ,  H01L29/51 ,  H01L29/517 ,  H01L29/518 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/66575 ,  H01L29/66772 ,  H01L29/78684

Abstract: A method of fabricating a MOSFET is provided, including: depositing an oxide layer on a silicon substrate for device isolation; forming a silicon based alloy island above a gate region in the substrate, wherein the silicon based alloy comprises a silicon germanium alloy or a silicon tin alloy or another alloy of Group IV-B elements; building a sidewall about the silicon based alloy island; forming a source region and a drain region in the substrate; removing the silicon based alloy island, thereby leaving a void over the gate region; filing the void and the areas over the source region and the drain region; and planarizing the upper surface of the structure by chemical mechanical polishing. Alternative embodiments providing conventional and raised source/drain structures are disclosed.

Abstract translation: 提供一种制造MOSFET的方法，包括：在硅衬底上沉积氧化层用于器件隔离; 在所述基板的栅极区域的上方形成硅基合金岛，其中所述硅基合金包含硅锗合金或硅锡合金或第IV-B族元素的另一种合金; 围绕硅基合金岛构建侧壁; 在衬底中形成源区和漏区; 去除硅基合金岛，从而在栅极区域上留下空隙; 填充空隙和源区域和漏区域上的区域; 并通过化学机械抛光对结构的上表面进行平面化。 公开了提供常规和凸起的源极/漏极结构的替代实施例。

公开(公告)号：US08259500B2

公开(公告)日：2012-09-04

申请号：US13034608

申请日：2011-02-24

Applicant: Yanjun Ma ,  Steven I. Mozsgai

Inventor： Yanjun Ma ,  Steven I. Mozsgai

IPC: G11C16/04

CPC classification number: G11C16/0433 ,  G11C16/20 ,  H01L21/28273 ,  H01L27/0207 ,  H01L27/11531 ,  H01L27/11534 ,  H01L29/42324 ,  H01L29/66825 ,  H01L29/7881

Abstract: A non-volatile memory (NVM) circuit is provided, that includes at least a first and second NVM sub-array. The first sub-array is built from first memory cells. The second NVM sub-array is built from second memory cells that are constructed differently from the first memory cells. The NVM sub-arrays share a support circuit. In some embodiments the sub-arrays can be constructed, so that they exhibit different characteristics tailored to their intended use. For example one sub-array might be tailored for data retention, while the next sub-array for programming endurance, still another for write disturb immunity.

Abstract translation: 提供了一种非易失性存储器（NVM）电路，其包括至少第一和第二NVM子阵列。 第一个子阵列是从第一个存储单元构建的。 第二NVM子阵列由与第一存储器单元不同的构造的第二存储器单元构建。 NVM子阵列共享支持电路。 在一些实施例中，可以构造子阵列，使得它们具有根据其预期用途定制的不同特征。 例如，一个子阵列可能被定制用于数据保留，而用于编程耐久性的下一个子阵列，还是另一个用于写干扰抗扰度的子阵列。

公开(公告)号：US07920423B1

公开(公告)日：2011-04-05

申请号：US12114574

申请日：2008-05-02

Applicant: Yanjun Ma ,  Steven I. Mozsgai

Inventor： Yanjun Ma ,  Steven I. Mozsgai

IPC: G11C16/04

CPC classification number: G11C16/0433 ,  G11C16/20 ,  H01L21/28273 ,  H01L27/0207 ,  H01L27/11531 ,  H01L27/11534 ,  H01L29/42324 ,  H01L29/66825 ,  H01L29/7881

Abstract: A non-volatile memory (NVM) circuit is provided, that includes at least a first and second NVM sub-array. The first sub-array is built from first memory cells. The second NVM sub-array is built from second memory cells that are constructed differently from the first memory cells. The NVM sub-arrays share a support circuit. In some embodiments the sub-arrays can be constructed, so that they exhibit different characteristics tailored to their intended use. For example one sub-array might be tailored for data retention, while the next sub-array for programming endurance, still another for write disturb immunity.

Abstract translation: 提供了一种非易失性存储器（NVM）电路，其包括至少第一和第二NVM子阵列。 第一个子阵列是从第一个存储单元构建的。 第二NVM子阵列由与第一存储器单元不同的构造的第二存储器单元构建。 NVM子阵列共享支持电路。 在一些实施例中，可以构造子阵列，使得它们具有根据其预期用途定制的不同特征。 例如，一个子阵列可能被定制用于数据保留，而用于编程耐久性的下一个子阵列，还是另一个用于写干扰抗扰度的子阵列。

公开(公告)号：US20060221715A1

公开(公告)日：2006-10-05

申请号：US11106982

申请日：2005-04-15

Applicant: Yanjun Ma ,  William Colleran ,  Vadim Gutnik

Inventor： Yanjun Ma ,  William Colleran ,  Vadim Gutnik

IPC: G11C7/10

CPC classification number: G11C29/789 ,  G11C29/76

Abstract: Two floating gate devices are arranged in a redundant configuration in a non-volatile memory (NVM) such that stress induced leakage current (SILC) or other failures do not result in a complete loss of memory storage. The redundant NVM may be arranged as a series configuration, a parallel configuration, a single-ended device, a differential device, a simple logic circuit function, a complex logic circuit function, and/or as part of an RFID tag system.

Abstract translation: 两个浮置栅极器件以非易失性存储器（NVM）中的冗余配置布置，使得应力诱发的漏电流（SILC）或其他故障不会导致存储器存储的完全丢失。 冗余NVM可以被布置为串联配置，并行配置，单端设备，差分设备，简单逻辑电路功能，复杂逻辑电路功能和/或作为RFID标签系统的一部分。

公开(公告)号：US06950342B2

公开(公告)日：2005-09-27

申请号：US10437262

申请日：2003-05-12

Applicant: Chad A. Lindhorst ,  Christopher J. Diorio ,  Troy N. Gilliland ,  Alberto Pesavento ,  Shail Srinivas ,  Yanjun Ma ,  Terry Hass ,  Kambiz Rahimi

Inventor： Chad A. Lindhorst ,  Christopher J. Diorio ,  Troy N. Gilliland ,  Alberto Pesavento ,  Shail Srinivas ,  Yanjun Ma ,  Terry Hass ,  Kambiz Rahimi

IPC: G11C16/04 ,  G11C20060101 ,  G11C5/00 ,  G11C7/06 ,  G11C11/34 ,  G11C16/02 ,  G11C16/06 ,  G11C16/28 ,  G11C16/34 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

CPC classification number: G11C16/0441 ,  G11C16/28 ,  G11C16/3468 ,  G11C16/3486 ,  G11C2216/10

Abstract: A number of designs for differential floating gate nonvolatile memories and memory arrays utilize differential pFET floating gate transistors to store information. Methods of implementing such memories and memory arrays together with methods of operation and test associated with such memories and memory arrays are presented.

Abstract translation: 用于差分浮置非易失性存储器和存储器阵列的许多设计利用差分pFET浮栅晶体管来存储信息。 提出了实现这种存储器和存储器阵列的方法以及与这种存储器和存储器阵列相关联的操作和测试方法。

公开(公告)号：US06620664B2

公开(公告)日：2003-09-16

申请号：US10072248

申请日：2002-02-07

Applicant: Yanjun Ma ,  Douglas James Tweet ,  David Russell Evans

Inventor： Yanjun Ma ,  Douglas James Tweet ,  David Russell Evans

IPC: H01L21338

CPC classification number: H01L29/66916 ,  H01L29/802

Abstract: An integrated circuit metal oxide semiconductor device comprises a gate region and a dielectric layer positioned therein, wherein the dielectric layer is substantially free of germanium diffused therein from a silicon germanium layer of the device. The method comprises depositing a dummy replacement gate, subjecting the device to high temperature processing, removing the dummy gate, and then depositing a dielectric material and a final gate material within the formed gate region. Because the dielectric material is deposited after high temperature processing of the device, there is negligible diffusion of germanium into the dielectric material.

Abstract translation: 集成电路金属氧化物半导体器件包括位于其中的栅极区域和电介质层，其中介电层基本上不含有从器件的硅锗层扩散的锗。 该方法包括沉积虚拟置换栅极，对器件进行高温处理，去除伪栅极，然后在所形成的栅极区域内沉积介电材料和最终栅极材料。 因为在器件的高温处理之后沉积介电材料，所以锗可以扩散到电介质材料中。

公开(公告)号：US06403453B1

公开(公告)日：2002-06-11

申请号：US09626837

申请日：2000-07-27

Applicant: Yoshi Ono ,  Yanjun Ma ,  Sheng Teng Hsu

Inventor： Yoshi Ono ,  Yanjun Ma ,  Sheng Teng Hsu

IPC: H01L2126

CPC classification number: H01L21/2236

Abstract: A method of plasma doping substrates is provided. The substrate is covered with photoresist and placed within a plasma chamber. A doping gas is introduced into the chamber and ionized. A dilutant gas is also introduced to provide better control of the total amount of dosage associated with a given duration of exposure. The dilutant gas is preferably monatomic to reduce, or eliminate, affects associated with pressure variations within the chamber caused by dissociation of elements within the plasma chamber. The dilutant gas preferably contains lighter elements so as to reduce, or eliminate, damage to the photoresist caused by ion impacts. The dilutant gas is preferably neon or helium. The present method provides a means to better control the dosage and reduce photoresist damage and contamination.

Abstract translation: 提供了一种等离子体掺杂衬底的方法。 衬底被光致抗蚀剂覆盖并置于等离子体室内。 将掺杂气体引入室并离子化。 还引入稀释气体以更好地控制与给定的暴露持续时间相关的剂量的总量。 稀释气体优选是单原子的，以减少或消除由等离子体室内的元素解离引起的室内压力变化的影响。 稀释气体优选含有较轻的元素，以便减少或消除由离子冲击引起的光致抗蚀剂的损伤。 稀释气体优选为氖气或氦气。 本方法提供了更好地控制剂量并减少光致抗蚀剂损伤和污染的方法。