公开(公告)号：US20090283827A1

公开(公告)日：2009-11-19

申请号：US12120158

申请日：2008-05-13

申请人： Sameer Pendharkar ,  Binghua Hu

发明人： Sameer Pendharkar ,  Binghua Hu

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/66712 ,  H01L21/26513 ,  H01L21/26586 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/086 ,  H01L29/1083 ,  H01L29/1095 ,  H01L29/66681 ,  H01L29/7809 ,  H01L29/7816

摘要： A LDMOS transistor having a channel region located between an outer boundary of an n-type region and an inner boundary of a p-body region. A width of the LDMOS channel region is less than 80% of a distance between an outer boundary of an n+-type region and the inner boundary of a p-body region. Also, a method for making a LDMOS transistor where the n-type dopants are implanted at an angle that is greater than an angle used to implant the p-type dopants. Furthermore, a VDMOS having first and second channel regions located between an inner boundary of a first and second p-body region and an outer boundary of an n-type region of the first and second p-body regions. The width of the first and second channel regions of the VDMOS is less than 80% of a distance between the inner boundary of the first and second p-body regions and an outer boundary of an n+-type region of the first and second p-body regions. Moreover, a method for making a VDMOS transistor where the n-type dopants are implanted at an angle that is greater than an angle used to implant the p-type dopants.

摘要翻译： 一种LDMOS晶体管，其具有位于n型区域的外边界和p体区域的内边界之间的沟道区域。 LDMOS通道区域的宽度小于n +型区域的外边界与p体区域的内边界之间的距离的80％。 此外，制造LDMOS晶体管的方法，其中n型掺杂剂以大于用于注入p型掺杂剂的角度的角度注入。 此外，VDMOS具有位于第一和第二p体区域的内边界和第一和第二p体区域的n型区域的外边界之间的第一和第二沟道区域。 VDMOS的第一和第二沟道区域的宽度小于第一和第二p体区域的内边界与第一和第二p体区域的n +型区域的外边界之间的距离的80％ 身体区域。 此外，制造VDMOS晶体管的方法，其中n型掺杂剂以大于用于注入p型掺杂剂的角度的角度注入。

公开(公告)号：US20060205140A1

公开(公告)日：2006-09-14

申请号：US11077074

申请日：2005-03-10

申请人： Bill Wofford ,  Blake Pasker ,  Xinfen Chen ,  Binghua Hu

发明人： Bill Wofford ,  Blake Pasker ,  Xinfen Chen ,  Binghua Hu

IPC分类号： H01L21/8242 ,  H01L21/20

CPC分类号： H01L28/40 ,  Y10S438/952

摘要： A capacitor (100) is disclosed that is formed as part of an integrated circuit (IC) fabrication process. The capacitor (100) has conductive top and bottom electrodes (140, 144) and a nonconductive capacitor dielectric (142). In one example, the dielectric (142) includes first and second thin dielectric layers (112, 114) that sandwich a layer of antireflective material (118). The thin layers (112, 114) provide the dielectric behavior necessary for the capacitor while the antireflective layer (118) promotes reduced feature sizes by mitigating reflected standing waves, among other things.

摘要翻译： 公开了作为集成电路（IC）制造工艺的一部分形成的电容器（100）。 电容器（100）具有导电的顶部和底部电极（140,144）和非导电电容器电介质（142）。 在一个示例中，电介质（142）包括夹着抗反射材料层（118）的第一和第二薄介电层（112,114）。 薄层（112,114）提供电容器所需的电介质行为，而抗反射层（118）除其他之外通过减轻反射的驻波来促进减小的特征尺寸。

公开(公告)号：US20070105332A1

公开(公告)日：2007-05-10

申请号：US11470023

申请日：2006-09-05

申请人： Bill Wofford ,  Blake Pasker ,  Xinfen Chen ,  Binghua Hu

发明人： Bill Wofford ,  Blake Pasker ,  Xinfen Chen ,  Binghua Hu

IPC分类号： H01L29/94 ,  H01L21/20

CPC分类号： H01L28/40 ,  Y10S438/952

摘要： A capacitor (100) is disclosed that is formed as part of an integrated circuit (IC) fabrication process. The capacitor (100) has conductive top and bottom electrodes (140, 144) and a nonconductive capacitor dielectric (142). In one example, the dielectric (142) includes first and second thin dielectric layers (112, 114) that sandwich a layer of antireflective material (118). The thin layers (112, 114) provide the dielectric behavior necessary for the capacitor while the antireflective layer (118) promotes reduced feature sizes by mitigating reflected standing waves, among other things.

摘要翻译： 公开了作为集成电路（IC）制造工艺的一部分形成的电容器（100）。 电容器（100）具有导电的顶部和底部电极（140,144）和非导电电容器电介质（142）。 在一个示例中，电介质（142）包括夹着抗反射材料层（118）的第一和第二薄介电层（112,114）。 薄层（112,114）提供电容器所需的电介质行为，而抗反射层（118）除其他之外通过减轻反射的驻波来促进减小的特征尺寸。

公开(公告)号：US08551886B2

公开(公告)日：2013-10-08

申请号：US12100118

申请日：2008-04-09

申请人： Kyle P. Hunt ,  Leila Elvira Noriega ,  Billy Alan Wofford ,  Asadd M. Hosein ,  Binghua Hu ,  Xinfen Chen

发明人： Kyle P. Hunt ,  Leila Elvira Noriega ,  Billy Alan Wofford ,  Asadd M. Hosein ,  Binghua Hu ,  Xinfen Chen

IPC分类号： H01L21/302 ,  H01L21/3105

CPC分类号： H01L21/31051 ,  H01L21/31053 ,  H01L21/31055 ,  H01L21/31056 ,  H01L21/76229 ,  H01L21/76232

摘要： A method for semiconductor processing is provided wherein a workpiece having an underlying body and a plurality of features extending therefrom, is provided. A first set of the plurality of features extend from the underlying body to a first plane, and a second set of the plurality features extend from the underlying body to a second plane. A protection layer overlies each of the plurality of features and an isolation layer overlies the underlying body and protection layer, wherein the isolation has a non-uniform first oxide density associated therewith. The isolation layer anisotropically etched based on a predetermined pattern, and then isotropically etched, wherein a second oxide density of the isolation layer is substantially uniform across the workpiece. The predetermined pattern is based, at least in part, on a desired oxide density, a location and extension of the plurality of features to the first and second planes.

摘要翻译： 提供了一种用于半导体处理的方法，其中具有下面的主体的工件和从其延伸的多个特征被提供。 所述多个特征的第一组从下面的本体延伸到第一平面，并且所述多个特征的第二组从下面的本体延伸到第二平面。 保护层覆盖多个特征中的每一个，并且隔离层覆盖下面的主体和保护层，其中隔离具有与其相关联的不均匀的第一氧化物密度。 基于预定图案各向异性蚀刻，然后各向同性蚀刻的隔离层，其中隔离层的第二氧化物密度在整个工件上基本均匀。 该预定图案至少部分地基于期望的氧化物密度，多个特征到第一和第二平面的位置和延伸。

公开(公告)号：US20110275168A1

公开(公告)日：2011-11-10

申请号：US12776057

申请日：2010-05-07

申请人： Eugene C. Davis ,  Binghua Hu ,  Sopa Chevacharoenkul ,  Prakash D. Dev

发明人： Eugene C. Davis ,  Binghua Hu ,  Sopa Chevacharoenkul ,  Prakash D. Dev

IPC分类号： H01L21/66 ,  H01L21/306

CPC分类号： C09G1/02 ,  H01L21/31053 ,  H01L21/3212 ,  H01L22/12 ,  H01L22/26

摘要： A one-step CMP process for polishing three or more layer film stacks on a wafer having a multilayer film stack thereon including a silicon nitride (SiNx) layer on its semiconductor surface, and a silicon oxide layer on the SiNx layer, wherein trench access vias extend through the silicon oxide layer and SiNx layer to trenches formed into the semiconductor surface, and wherein a polysilicon layer fills the trench access vias, fills the trenches, and is on the silicon oxide layer. CMP polishes the multilayer film stack with a slurry including slurry particles including at least one of silica and ceria. The CMP provides a removal rate (RR) for the polysilicon layer>a RR for the silicon oxide layer>a RR for the SiNx layer. The CMP process is continued to remove the polysilicon layer, silicon oxide layer and a portion of the SiNx layer to stop on the SiNx layer. Optical endpointing during CMP can provide a predetermined remaining thickness range for the SiNx layer.

摘要翻译： 一种用于在其上具有多层膜堆叠的晶片上的三层或更多层膜堆叠的半导体表面上的氮化硅（SiNx）层和SiN x层上的氧化硅层的一步CMP工艺，其中沟槽通孔 延伸穿过硅氧化物层和SiNx层到形成半导体表面的沟槽，并且其中多晶硅层填充沟槽接通通孔，填充沟槽并且在氧化硅层上。 CMP用包括二氧化硅和二氧化铈中的至少一种的浆料颗粒的浆料抛光多层膜堆叠。 CMP提供多晶硅层的去除率（RR）>硅氧化物层的RR> SiNx层的RR。 继续进行CMP处理以去除SiN x层上的多晶硅层，氧化硅层和SiNx层的一部分。 CMP期间的光学终点可以为SiNx层提供预定的剩余厚度范围。

公开(公告)号：US20070298579A1

公开(公告)日：2007-12-27

申请号：US11474824

申请日：2006-06-26

申请人： Binghua Hu ,  Yu-En Hsu ,  Qingfeng Wang

发明人： Binghua Hu ,  Yu-En Hsu ,  Qingfeng Wang

IPC分类号： H01L21/331 ,  H01L21/425

CPC分类号： H01L21/74 ,  H01L21/2253 ,  H01L21/8249 ,  H01L29/66272

摘要： A method for forming a bipolar transistor device includes providing a semiconductor substrate. An oxide layer is formed on the semiconductor substrate. The oxide layer is patterned to form an opening that exposes a portion of the semiconductor substrate. A dopant, such as antimony, is implanted into the semiconductor substrate through the opening to form a buried layer. An upper portion of the mask layer is removed to define a thin mask layer. A buried layer diffusion process is performed to drive in the implanted dopants while mitigating recess formation.

摘要翻译： 一种用于形成双极晶体管器件的方法包括提供半导体衬底。 在半导体基板上形成氧化物层。 图案化氧化物层以形成露出半导体衬底的一部分的开口。 通过开口将诸如锑的掺杂剂注入到半导体衬底中以形成掩埋层。 去除掩模层的上部以限定薄掩模层。 进行掩埋层扩散处理以在注入的掺杂剂中驱动，同时减轻凹陷形成。

公开(公告)号：US20070281433A1

公开(公告)日：2007-12-06

申请号：US11422221

申请日：2006-06-05

申请人： Martin Mollat ,  Tathagata Chatterjee ,  Henry L. Edwards ,  Lance S. Robertson ,  Richard B. Irwin ,  Binghua Hu

发明人： Martin Mollat ,  Tathagata Chatterjee ,  Henry L. Edwards ,  Lance S. Robertson ,  Richard B. Irwin ,  Binghua Hu

IPC分类号： H01L21/20

CPC分类号： H01L29/866 ,  H01L21/26506 ,  H01L29/66098

摘要： The present invention provides a method for manufacturing a semiconductor device. In one embodiment, the method for manufacturing the semiconductor device includes a method for manufacturing a zener diode, including among others, forming a doped well within a substrate and forming a suppression implant within the substrate. The method for manufacturing the zener diode may further include forming a cathode and an anode within the substrate, wherein the suppression implant is located proximate the doped well and configured to reduce threading dislocations.

摘要翻译： 本发明提供一种制造半导体器件的方法。 在一个实施例中，制造半导体器件的方法包括制造齐纳二极管的方法，其包括在衬底内形成掺杂阱并在衬底内形成抑制注入。 用于制造齐纳二极管的方法还可以包括在衬底内形成阴极和阳极，其中抑制植入物位于掺杂阱附近并且被配置为减少穿透位错。

公开(公告)号：US06806541B2

公开(公告)日：2004-10-19

申请号：US10791172

申请日：2004-03-01

申请人： Lily X. Springer ,  Binghua Hu ,  Chin-Yu Tsai ,  Jozef C. Mitros

发明人： Lily X. Springer ,  Binghua Hu ,  Chin-Yu Tsai ,  Jozef C. Mitros

IPC分类号： H01L2976

CPC分类号： H01L21/76216

摘要： An electronic device architecture is described comprising a field effect device in an active region 22 of a substrate 10. Channel stop implant regions 28a and 28b are used as isolation structures and are spaced apart from the active region 22 by extension zones 27a and 27b. The spacing is established by using an inner mask layer 20 and an outer mask layer 26 to define the isolation structures.

公开(公告)号：US07829430B2

公开(公告)日：2010-11-09

申请号：US11968085

申请日：2007-12-31

申请人： Sameer Pendharker ,  Binghua Hu

发明人： Sameer Pendharker ,  Binghua Hu

IPC分类号： H01L21/762 ,  H01L21/3213

CPC分类号： H01L21/761 ,  H01L21/823878 ,  H01L21/823892 ,  H01L27/0207

摘要： Devices and methods are presented to fabricate dummy moats in an isolation region on a substrate. Presently, dummy moats are prone to losing impedance after the silicidation process. In high-voltage devices, silicided dummy moats reduce the breakdown voltage between active regions, particularly when the dummy moat overlaps or is in close proximity to a junction. The present devices and methods disclose a dummy moat covered with an oxide layer. During the silicidation process, the dummy moat and other designated isolation regions remain non-silicided. Thus, high and stable breakdown voltages are maintained.

摘要翻译： 提供了设备和方法以在衬底上的隔离区域中制造虚设的护城河。 目前，在硅化处理之后，假山羊容易失去阻抗。 在高压设备中，硅化虚拟护城河降低了活性区域之间的击穿电压，特别是当虚拟护套重叠或接近结点时。 本发明的装置和方法公开了覆盖有氧化物层的虚拟护城河。 在硅化过程中，虚拟护城河和其他指定的隔离区域保持非硅化。 因此，保持高且稳定的击穿电压。

公开(公告)号：US07785974B2

公开(公告)日：2010-08-31

申请号：US11474824

申请日：2006-06-26

申请人： Binghua Hu ,  Yu-En Hsu ,  Qingfeng Wang

发明人： Binghua Hu ,  Yu-En Hsu ,  Qingfeng Wang

IPC分类号： H01L21/331

CPC分类号： H01L21/74 ,  H01L21/2253 ,  H01L21/8249 ,  H01L29/66272

摘要： A method for forming a bipolar transistor device includes providing a semiconductor substrate. An oxide layer is formed on the semiconductor substrate. The oxide layer is patterned to form an opening that exposes a portion of the semiconductor substrate. A dopant, such as antimony, is implanted into the semiconductor substrate through the opening to form a buried layer. An upper portion of the mask layer is removed to define a thin mask layer. A buried layer diffusion process is performed to drive in the implanted dopants while mitigating recess formation.

摘要翻译： 一种用于形成双极晶体管器件的方法包括提供半导体衬底。 在半导体基板上形成氧化物层。 图案化氧化物层以形成露出半导体衬底的一部分的开口。 通过开口将诸如锑的掺杂剂注入到半导体衬底中以形成掩埋层。 去除掩模层的上部以限定薄掩模层。 进行掩埋层扩散处理以在注入的掺杂剂中驱动，同时减轻凹陷形成。