公开(公告)号：US07820504B2

公开(公告)日：2010-10-26

申请号：US10890529

申请日：2004-07-12

申请人： Daniela Brazzelli ,  Livio Baldi ,  Giorgio Servalli

发明人： Daniela Brazzelli ,  Livio Baldi ,  Giorgio Servalli

IPC分类号： H01L21/8238 ,  H01L27/108

CPC分类号： H01L21/76229

摘要： Embodiments of this invention relate to a method for manufacturing isolation structures with different depths in a monolithically integrated semiconductor electronic device. An inventive method according to an embodiment of the invention comprises a first step of defining active areas on a semiconductor material substrate, a second step of forming isolation structures by realising trenches in said substrate and then filling them with field oxide, a third step of defining lithographically at least a first device area, and a fourth step of realising a digging in the substrate and in the field oxide of said first device area.

摘要翻译： 本发明的实施例涉及一种用于在单片集成半导体电子器件中制造具有不同深度的隔离结构的方法。 根据本发明实施例的发明方法包括：在半导体材料衬底上限定有源区的第一步骤;通过在所述衬底中实现沟槽然后用场氧化物填充来形成隔离结构的第二步骤;第三步骤， 光刻至少第一装置区域，以及第四步骤，在所述基板和所述第一装置区域的场氧化物中实现挖掘。

公开(公告)号：US07125808B2

公开(公告)日：2006-10-24

申请号：US10749020

申请日：2003-12-29

申请人： Cesare Clementi ,  Alessia Pavan ,  Livio Baldi

发明人： Cesare Clementi ,  Alessia Pavan ,  Livio Baldi

IPC分类号： H01L21/302 ,  H01B13/00

CPC分类号： H01L27/11521 ,  H01L27/115

摘要： A method is described for manufacturing non-volatile memory cells on a semiconductive substrate having active areas bounded by portions of an insulating layer. A thin layer of tunnel oxide is formed and a first layer of conductive material is then deposited. A plurality of floating gate regions are defined by forming stripes of shielding material only above pairs of alternated active areas. Spacers of a selective material are defined with respect to the shielding material and of small width at will in the shelter of the side walls of the stripes thus defined. A shielding material is also deposited on the active areas which lacked it. The formation of the floating gate is completed by leaving the definition of the distance between the floating gate regions to the spacers.

摘要翻译： 描述了一种用于在具有由绝缘层的部分界定的有源区域的半导体衬底上制造非易失性存储器单元的方法。 形成隧道氧化物的薄层，然后沉积第一层导电材料。 通过仅在交替的有效区域对之上形成屏蔽材料条来限定多个浮动栅极区域。 选择性材料的间隔相对于屏蔽材料限定，并且在如此限定的条纹的侧壁的遮蔽物中随意地被限定。 屏蔽材料也沉积在缺乏它的有源区上。 通过将浮动栅极区域之间的距离定义为间隔物来完成浮栅的形成。

公开(公告)号：US06747309B2

公开(公告)日：2004-06-08

申请号：US10123507

申请日：2002-04-15

申请人： Livio Baldi ,  Maurelli Alfonso

发明人： Livio Baldi ,  Maurelli Alfonso

IPC分类号： H01L29788

CPC分类号： H01L27/11526 ,  H01L27/105 ,  H01L27/11539 ,  H01L27/11546

摘要： A method of manufacturing an integrated semiconductor device having at least one non-volatile floating gate memory cell and at least one logic transistor. The method includes growing a first gate oxide layer over a silicon substrate, depositing a first polysilicon layer over the first gate oxide layer, selectively etching and removing the first polysilicon layer in order to define the floating gate of the memory cell, introducing dopant in order to obtain source and drain regions of the memory cell, depositing a dielectric layer, selectively etching and removing the dielectric layer and the first polysilicon layer in a region wherein the logic transistor will be formed, depositing a second polysilicon layer, selectively etching and removing the second polysilicon layer in order to define the gate of the logic transistor and the control gate of the memory cell. Between selectively etching the dielectric and depositing a second polysilicon layer, a first sub-step of removing the first gate oxide layer in the region for the logic transistor, and a second sub-step of growing a second oxide gate layer over the region, the second gate oxide layer having a different thickness than the first gate oxide layer.

摘要翻译： 一种制造具有至少一个非易失性浮动栅极存储单元和至少一个逻辑晶体管的集成半导体器件的方法。 该方法包括在硅衬底上生长第一栅极氧化层，在第一栅极氧化物层上沉积第一多晶硅层，选择性地蚀刻和去除第一多晶硅层，以便限定存储单元的浮置栅极，按顺序引入掺杂剂 为了获得存储单元的源极和漏极区域，沉积介电层，在将形成逻辑晶体管的区域中选择性地蚀刻和去除电介质层和第一多晶硅层，沉积第二多晶硅层，选择性地蚀刻和去除 第二多晶硅层，以便限定逻辑晶体管的栅极和存储器单元的控制栅极。 在选择性地蚀刻电介质并沉积第二多晶硅层之间，去除用于逻辑晶体管的区域中的第一栅极氧化物层的第一子步骤以及在该区域上生长第二氧化物栅极层的第二子步骤， 第二栅极氧化物层具有与第一栅极氧化物层不同的厚度。

公开(公告)号：US06547151B1

公开(公告)日：2003-04-15

申请号：US09645008

申请日：2000-08-23

申请人： Livio Baldi

发明人： Livio Baldi

IPC分类号： G06K1906

CPC分类号： G06K19/07749 ,  G07D7/01

摘要： A currency note includes an identification and/or authentication element including an integrated circuit. The integrated circuit can store, securely in electronic form and accessible from outside, such information as: the value, serial number, issuer, and date of issuance.

摘要翻译： 货币包括包括集成电路的识别和/或认证元件。 集成电路可以安全地以电子形式存储，并可从外部存取以下信息：价值，序列号，发行人和发行日期。

公开(公告)号：US06350676B1

公开(公告)日：2002-02-26

申请号：US08411385

申请日：1995-03-28

申请人： Livio Baldi

发明人： Livio Baldi

IPC分类号： H01L214763

CPC分类号： H01L21/76843 ,  H01L21/32136 ,  H01L21/76865 ,  H01L21/76877

摘要： A method of forming high-stability metallic contacts in an integrated circuit with one or more metallized layers wherein, after a preliminary step of providing contact holes in a layer of dielectric material: a prebarrier layer of Ti or TiN is formed overall; a layer of tungsten is formed by chemical vapor deposition so as to coat the bases and the walls of the contact holes uniformly; aluminum or an alloy thereof is sputter-deposited, under high-temperature low-flux conditions, to fill the contact holes; and patterning the aluminum and tungsten layers to form metallic interconnections of predetermined geometry.

摘要翻译： 在具有一个或多个金属化层的集成电路中形成高稳定性金属触点的方法，其中在介电材料层中提供接触孔的预备步骤：整体形成Ti或TiN的预阻隔层; 通过化学气相沉积形成钨层，以均匀地涂覆接触孔的基体和壁; 铝或其合金在高温低通量条件下溅射沉积以填充接触孔; 以及图案化铝和钨层以形成预定几何形状的金属互连。

公开(公告)号：US06061269A

公开(公告)日：2000-05-09

申请号：US613443

申请日：1996-03-04

申请人： Livio Baldi ,  Paola Paruzzi

发明人： Livio Baldi ,  Paola Paruzzi

IPC分类号： H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  G11C16/04

CPC分类号： H01L29/7885

摘要： The present invention concerns an electrically programmable and erasable non-volatile memory cell having a traditional structure but being inverted in the conductivity type of the component elements and lacking the second source diffusion.

摘要翻译： 本发明涉及一种电可编程和可擦除的非易失性存储单元，其具有传统结构，但在组分元件的导电类型中被反转，并且缺少第二源扩散。

公开(公告)号：US6036566A

公开(公告)日：2000-03-14

申请号：US942477

申请日：1997-10-02

申请人： Livio Baldi ,  Maria Santina Marangon

发明人： Livio Baldi ,  Maria Santina Marangon

IPC分类号： H01J1/304 ,  H01J9/02 ,  H01J29/04 ,  H01J31/12 ,  H01L29/66

CPC分类号： H01J9/025 ,  H01J1/3042

摘要： The microtips of charge emitting material, which define the cathode of the flat FED screen and face the grid of the screen, are tubular and have portions with a small radius of curvature. The microtips are obtained by forming openings in the dielectric layer separating the cathode connection layer from the grid layer, depositing a conducting material layer to cover the walls of the openings, and anisotropically etching the layer of conducting material to form inwardly-inclined surfaces with emitting tips. Subsequently, the portions of the dielectric layer surrounding the microtips are removed.

摘要翻译： 限定平面FED屏幕的阴极并且面对屏幕的栅格的电荷发射材料的微尖端是管状的并且具有小的曲率半径的部分。 微尖端通过在将阴极连接层与栅格层分隔开的电介质层中形成开口，沉积导电材料层以覆盖开口的壁而获得，并各向异性地蚀刻导电材料层以形成具有发射的向内倾斜表面 提示。 随后，去除围绕微尖头的电介质层的部分。

公开(公告)号：US5847504A

公开(公告)日：1998-12-08

申请号：US690895

申请日：1996-08-01

申请人： Livio Baldi

发明人： Livio Baldi

IPC分类号： G09G3/22 ,  H01J1/304 ,  H01J31/12 ,  H01J1/62 ,  H01J1/02 ,  H01J1/16 ,  H01J63/04

CPC分类号： G09G3/22 ,  H01J1/3042 ,  H01J31/127 ,  H01J2201/30403 ,  H01J2201/319 ,  H01J2329/00

摘要： A pixel emission current limiting resistance is realized by forming a stack of alternately doped amorphous or polycrystalline silicon layers over the cathodic conductors of a FED driving matrix. The stack of amorphous or polycrystalline silicon layers doped alternately n and p provides at least a reversely biased n/p junction having a leakage current that matches the required level of pixel emission current. The reversely biased junction constitutes a nonlinear series resistance that is quite effective in limiting the emission current through any one of the microtips that form an individually excitable pixel and which are formed on the uppermost layer of the stack.

摘要翻译： 通过在FED驱动矩阵的阴极导体上形成交替掺杂的非晶或多晶硅层的堆叠来实现像素发射电流限制电阻。 掺杂交替地n和p的非晶或多晶硅层的堆叠提供至少一个具有与所要求的像素发射电流水平匹配的漏电流的反向偏置n / p结。 反向偏置的结构成非线性串联电阻，其非常有效地限制通过形成可单独激发的像素并且形成在堆叠的最上层上的任何一个微尖端的发射电流。

公开(公告)号：US5818760A

公开(公告)日：1998-10-06

申请号：US871226

申请日：1997-06-09

申请人： Livio Baldi ,  Federico Pio

发明人： Livio Baldi ,  Federico Pio

IPC分类号： G11C17/00 ,  G11C16/06 ,  G11C16/12 ,  G11C16/30 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  G11C7/00

CPC分类号： G11C16/30 ,  G11C16/12

摘要： A programming voltage is supplied to a control gate of a non-volatile memory cell via a control gate line. A supply voltage is coupled to a first plate of a capacitor and a reference voltage is coupled to a second plate of the capacitor. The supply voltage is then uncoupled from the first plate and the reference voltage is uncoupled from the second plate. Next, the reference voltage is coupled to the first plate to generate the programming voltage on the second plate.

公开(公告)号：US5817557A

公开(公告)日：1998-10-06

申请号：US792893

申请日：1997-01-31

申请人： Livio Baldi

发明人： Livio Baldi

IPC分类号： H01L21/336 ,  H01L21/8247

CPC分类号： H01L29/66825 ,  Y10S438/981

摘要： A process including the steps of forming a gate oxide layer on a semiconductor substrate; masking the gate oxide layer with a nitride mask forming openings in the gate oxide layer using the nitride mask; and forming, at the openings, tunnel oxide regions of a thickness smaller than the thickness of the gate oxide layer. The nitride mask presents a thickness smaller than the width of the openings to improve etching of the gate oxide layer and subsequent washing. The mask also protects the covered layers when etching the gate oxide and growing the tunnel oxide regions, and is removed easily without damaging the exposed layers.

摘要翻译： 一种方法，包括在半导体衬底上形成栅极氧化层的步骤; 使用氮化物掩模，用栅极氧化物层中的氮化物掩模掩蔽栅极氧化物层; 并且在所述开口处形成厚度小于所述栅极氧化物层的厚度的隧道氧化物区域。 氮化物掩模的厚度小于开口的宽度，以改善栅极氧化物层的蚀刻和随后的洗涤。 当蚀刻栅极氧化物并生长隧道氧化物区域时，掩模还保护被覆层，并且容易地去除而不损坏暴露的层。