公开(公告)号：US20050042812A1

公开(公告)日：2005-02-24

申请号：US10890529

申请日：2004-07-12

申请人： Daniela Brazzelli ,  Livio Baldi ,  Giorgio Servalli

发明人： Daniela Brazzelli ,  Livio Baldi ,  Giorgio Servalli

IPC分类号： H01L21/762 ,  H01L21/8238

CPC分类号： H01L21/76229

摘要： Embodiments of this invention relate to a method for manufacturing isolation structures with different depths in a monolithically integrated semiconductor electronic device. An inventive method according to an embodiment of the invention comprises a first step of defining active areas on a semiconductor material substrate, a second step of forming isolation structures by realising trenches in said substrate and then filling them with field oxide, a third step of defining lithographically at least a first device area, and a fourth step of realising a digging in the substrate and in the field oxide of said first device area.

摘要翻译： 本发明的实施例涉及一种用于在单片集成半导体电子器件中制造具有不同深度的隔离结构的方法。 根据本发明实施例的发明方法包括：在半导体材料衬底上限定有源区的第一步骤;通过在所述衬底中实现沟槽然后用场氧化物填充来形成隔离结构的第二步骤;第三步骤， 光刻至少第一装置区域，以及第四步骤，在所述基板和所述第一装置区域的场氧化物中实现挖掘。

公开(公告)号：US07820504B2

公开(公告)日：2010-10-26

申请号：US10890529

申请日：2004-07-12

申请人： Daniela Brazzelli ,  Livio Baldi ,  Giorgio Servalli

发明人： Daniela Brazzelli ,  Livio Baldi ,  Giorgio Servalli

IPC分类号： H01L21/8238 ,  H01L27/108

CPC分类号： H01L21/76229

摘要： Embodiments of this invention relate to a method for manufacturing isolation structures with different depths in a monolithically integrated semiconductor electronic device. An inventive method according to an embodiment of the invention comprises a first step of defining active areas on a semiconductor material substrate, a second step of forming isolation structures by realising trenches in said substrate and then filling them with field oxide, a third step of defining lithographically at least a first device area, and a fourth step of realising a digging in the substrate and in the field oxide of said first device area.

摘要翻译： 本发明的实施例涉及一种用于在单片集成半导体电子器件中制造具有不同深度的隔离结构的方法。 根据本发明实施例的发明方法包括：在半导体材料衬底上限定有源区的第一步骤;通过在所述衬底中实现沟槽然后用场氧化物填充来形成隔离结构的第二步骤;第三步骤， 光刻至少第一装置区域，以及第四步骤，在所述基板和所述第一装置区域的场氧化物中实现挖掘。

公开(公告)号：US06465950B1

公开(公告)日：2002-10-15

申请号：US09482244

申请日：2000-01-13

申请人： Livio Baldi ,  Maria Santina Marangon

发明人： Livio Baldi ,  Maria Santina Marangon

IPC分类号： H01J6302

CPC分类号： H01J9/025 ,  H01J1/3042

摘要： The microtips of charge emitting material, which define the cathode of the flat FED screen and face the grid of the screen, are tubular and have portions with a small radius of curvature. The microtips are obtained by forming openings in the dielectric layer separating the cathode connection layer from the grid layer, depositing a conducting material layer to cover the walls of the openings, and anisotropically etching the layer of conducting material to form inwardly-inclined surfaces with emitting tips. Subsequently, the portions of the dielectric layer surrounding the microtips are removed.

摘要翻译： 限定平面FED屏幕的阴极并且面对屏幕的栅格的电荷发射材料的微尖端是管状的并且具有小的曲率半径的部分。 微尖端通过在将阴极连接层与栅格层分隔开的电介质层中形成开口，沉积导电材料层以覆盖开口的壁而获得，并各向异性地蚀刻导电材料层以形成具有发射的向内倾斜表面 提示。 随后，去除围绕微尖头的电介质层的部分。

公开(公告)号：US6000980A

公开(公告)日：1999-12-14

申请号：US807113

申请日：1996-12-13

申请人： Livio Baldi ,  Alessandro Tonti

发明人： Livio Baldi ,  Alessandro Tonti

IPC分类号： H01J9/02

CPC分类号： H01J9/025 ,  H01J2201/319

摘要： A process for forming a microtip cathode structure on a field emission display panel which avoids the need of vacuum depositing a lift-off layer for the microtip deposition overstructure in specially equipped reactors to accomplish a deposition at a grazing angle, by co-patterening the lift-off layer together with an underlying metal grid layer using a succession of different etching steps through the openings of a grid definition mask. According to an embodiment, nickel is used as lift-off material and is either wet-etched or sputter-etched before performing a plasma etch of the underlying grid metal layer. According to an alternative embodiment, the masking resist layer is used as lift-off material.

摘要翻译： 一种用于在场发射显示面板上形成微尖端阴极结构的方法，其避免真空沉积用于特别装备的反应器中的微尖端沉积过度结构的剥离层，以通过共同观察电梯来实现放电角度的沉积 使用一系列不同的蚀刻步骤通过网格定义掩模的开口与底层金属网格层一起使用。 根据一个实施例，镍用作剥离材料，并且在对下面的栅格金属层进行等离子体蚀刻之前被湿式蚀刻或溅射蚀刻。 根据替代实施例，掩模抗蚀剂层用作剥离材料。

公开(公告)号：US5589701A

公开(公告)日：1996-12-31

申请号：US486747

申请日：1995-06-07

申请人： Livio Baldi

发明人： Livio Baldi

IPC分类号： H01L21/8238 ,  H01L29/76

CPC分类号： H01L21/823842

摘要： A process for forming low threshold voltage P-channel MOS transistors in semiconductor integrated circuits for analog applications, said circuits including high resistivity resistors formed in a layer of polycrystalline silicon and N-channel MOS transistors having active areas which have been obtained by implantation in a P-type well, comprises the steps of,providing a first mask over both said resistors and the semiconductor regions where the low threshold voltage P-channel transistors are to be formed,doping the polycrystalline layer uncovered by said first mask,providing a second mask for protecting the resistors and the semiconductor regions where said low threshold voltage P-channel transistors are to be formed, andN+ implanting the active areas of the N-channel transistors.

摘要翻译： 一种用于在用于模拟应用的半导体集成电路中形成低阈值电压P沟道MOS晶体管的工艺，所述电路包括形成在多晶硅层中的高电阻率电阻器和具有有源区域的N沟道MOS晶体管，所述有源区域已经通过 P型阱包括以下步骤：在所述电阻器和要形成低阈值电压P沟道晶体管的半导体区域上提供第一掩模，掺杂未被所述第一掩模覆盖的多晶层，提供第二掩模 用于保护要形成所述低阈值电压P沟道晶体管的电阻器和半导体区域，以及N +注入N沟道晶体管的有源区域。

公开(公告)号：US4816883A

公开(公告)日：1989-03-28

申请号：US64480

申请日：1987-06-22

申请人： Livio Baldi

发明人： Livio Baldi

IPC分类号： H01L21/8247 ,  H01L21/8246 ,  H01L27/112 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  H01L29/78 ,  G11C11/34 ,  H01L27/02

CPC分类号： H01L29/7885 ,  H01L27/115

摘要： A nonvolatile, EPROM type memory cell, formed using a p-channel MOS device instead of an n-channel MOS device as customary according to the prior art, offers several advantages: improved programming characteristics, a relatively low gate voltage for writing, a lower power dissipation and above all compatability with the great majority of CMOS fabrication processes. An explanation of such surprising characteristics may be attributed to more favorable conditions of electric field during programming, i.e. during charging of the floating gate, in respect to those existing in the case of the conventional n-channel memory cell.

摘要翻译： 使用根据现有技术的通常使用p沟道MOS器件代替n沟道MOS器件的非易失性EPROM型存储单元提供了几个优点：改进的编程特性，用于写入的相对较低的栅极电压，较低的 功耗以及绝大多数CMOS制造工艺的兼容性。 关于这种令人惊奇的特性的解释可以归因于在编程期间，即在对浮动栅极充电期间相对于在常规n沟道存储单元的情况下存在的电场的更有利的条件。

公开(公告)号：US07125807B2

公开(公告)日：2006-10-24

申请号：US10746878

申请日：2003-12-23

申请人： Cesare Clementi ,  Alessia Pavan ,  Livio Baldi

发明人： Cesare Clementi ,  Alessia Pavan ,  Livio Baldi

IPC分类号： H01L21/302 ,  H01B13/00

CPC分类号： H01L27/11521 ,  H01L27/115

摘要： A semiconductor substrate has active areas bounded by portions of an insulating layer. A thin layer of tunnel oxide is formed on the substrate and a first layer of conductive material is then deposited. Non-volatile memory cells are manufactured thereon by defining floating gate regions. The definition of these floating gate regions involves defining the first layer of conductive material in order to form a plurality of alternated stripes above pairs of active areas alternated by active areas lacking stripes. Spacers are then formed in the shelter of the side walls of the alternated stripes. A second layer of conductive material is then deposited together with the first layer of conductive material. The spacers are then selectively removed.

摘要翻译： 半导体衬底具有由绝缘层的部分限定的有源区域。 在衬底上形成隧道氧化物薄层，然后沉积第一层导电材料。 通过限定浮动栅极区域在其上制造非易失性存储器单元。 这些浮动栅极区域的定义涉及限定第一层导电材料，以便形成由有缺陷条纹的有源区域交替的一对有源区域之上的多个交替条纹。 然后在交替条纹的侧壁的遮蔽物中形成间隔物。 然后第二层导电材料与第一层导电材料一起沉积。 然后选择性地去除间隔物。

公开(公告)号：US06188121B1

公开(公告)日：2001-02-13

申请号：US09119115

申请日：1998-07-20

申请人： Livio Baldi ,  Paolo Ghezzi ,  Alfonso Maurelli

发明人： Livio Baldi ,  Paolo Ghezzi ,  Alfonso Maurelli

IPC分类号： H01L2900

CPC分类号： H01L28/60 ,  H01L27/0805 ,  H01L29/94

摘要： A high voltage capacitor, integratable monolithically on a semiconductor substrate which accommodates a field oxide region overlaid by a first layer of polycrystalline silicon isolated from a second layer of polycrystalline silicon by an interpoly dielectric layer, comprises two elementary capacitors having a first common conductive plate which is formed in the first layer of polycrystalline silicon. Each of these elementary capacitors has a second conductive plate formed in the second layer of polycrystalline silicon above the first plate, and includes said interpoly dielectric layer as an isolation dielectric between the two plates.

摘要翻译： 一个高电压电容器，整体地集成在半导体衬底上，该半导体衬底上容纳由第二层多晶硅隔绝的第一多晶硅层覆盖的场氧化物区域，该第二层由多晶硅电介质层隔开，包括两个基本电容器，其具有第一公共导电板， 形成在第一层多晶硅中。 这些基本电容器中的每一个具有形成在第一板上方的第二多晶硅层中的第二导电板，并且包括作为两个板之间的隔离电介质的所述互聚电介质层。

公开(公告)号：US4897365A

公开(公告)日：1990-01-30

申请号：US124440

申请日：1987-11-23

申请人： Livio Baldi ,  Daniela Beardo ,  Marco Icardi ,  Adriana Rebora

发明人： Livio Baldi ,  Daniela Beardo ,  Marco Icardi ,  Adriana Rebora

IPC分类号： H01L21/76 ,  H01L21/302 ,  H01L21/3065 ,  H01L21/311 ,  H01L21/316 ,  H01L21/762

CPC分类号： H01L21/31116 ,  H01L21/76202 ,  Y10S148/117 ,  Y10S148/131

摘要： A method for reducing birdbeaks formed during a planox process is disclosed. On a silicon substrate (1), oxide (2) and nitride (3) are formed. The oxide and nitride are then selectively etched using a single plasma having high selectivity with respect to silicon and a photoresist mask (4). The high selectivity toward silicon is achieved by use of a CHF.sub.3 +CO.sub.2 plasma under conditions of 30:1 oxide/silicon selectivity. Field oxide regions (5) with reduced birdbeaks can then be formed.

摘要翻译： 公开了一种减少在平面过程中形成的鸟鸣的方法。 在硅衬底（1）上形成氧化物（2）和氮化物（3）。 然后使用相对于硅和光致抗蚀剂掩模（4）具有高选择性的单个等离子体来选择性地蚀刻氧化物和氮化物。 对硅的高选择性通过在30:1氧化物/硅选择性的条件下使用CHF 3 + CO 2等离子体来实现。 然后可以形成具有减小的鸟喙的场氧化物区域（5）。

公开(公告)号：US4703552A

公开(公告)日：1987-11-03

申请号：US689875

申请日：1985-01-09

申请人： Livio Baldi ,  Giuseppe Corda ,  Giulio Iannuzzi ,  Danilo Re ,  Giorgio De Santi

发明人： Livio Baldi ,  Giuseppe Corda ,  Giulio Iannuzzi ,  Danilo Re ,  Giorgio De Santi

IPC分类号： H01L27/092 ,  H01L21/8238 ,  H01L29/49 ,  H01L29/78 ,  H01L21/265 ,  H01L21/28

CPC分类号： H01L29/4933 ,  H01L21/823835 ,  Y10S148/082

摘要： The method provides for the formation of a layer of metal silicide on the gate layer of polycrystalline silicon and, for each transistor of the CMOS pair, the simultaneous doping of the active regions and the gate polycrystalline silicon. In the structure produced by this method, the gate electrodes are of polycrystalline silicon covered by metal silicide and the gate electrode of the n-channel transistor is doped with n-type material, while the gate electrode of the p-channel transistor is doped with p-type impurities. This enables the production of low threshold voltages for both transistors even in the case of very high integration densities.

摘要翻译： 该方法提供在多晶硅的栅极层上形成金属硅化物层，并且对于CMOS对的每个晶体管，同时掺杂有源区和栅极多晶硅。 在通过该方法制造的结构中，栅电极是由金属硅化物覆盖的多晶硅，并且n沟道晶体管的栅电极掺杂有n型材料，而p沟道晶体管的栅电极掺杂 p型杂质。 这使得即使在非常高的集成密度的情况下也可以为两个晶体管产生低阈值电压。