公开(公告)号：US06385396B1

公开(公告)日：2002-05-07

申请号：US09426963

申请日：1999-10-26

Applicant: Chee-Wee Liu ,  Min-Hung Lee

Inventor： Chee-Wee Liu ,  Min-Hung Lee

IPC: H01L21205

CPC classification number: H01L21/67115

Abstract: A reflector structure is provided for improving irradiation uniformity of a linear lamp array applied in a semiconductor process. The reflector structure includes a central reflector, two side reflectors, and two inclined reflectors. The central reflector is horizontally set above the linear lamp array at a first predetermined distance from a wafer for reflecting light irradiated from a central part of the linear lamp array to the wafer. The two side reflectors are horizontally set above the linear lamp at a second predetermined distance to the wafer, wherein the second predetermined distance is less than the first predetermined distance, and respectively connected to two opposite side parts of the central reflector for reflecting light irradiated from side parts of the linear lamp array to the wafer. The two inclined reflectors are respectively connected to one side of each of the two first side reflectors at an inclined angel to the wafer for reflecting light irradiated from two end parts of the linear lamp array to the wafer.

Abstract translation: 提供了一种用于改善在半导体工艺中应用的线性灯阵列的照射均匀性的反射器结构。 反射器结构包括中央反射器，两个侧反射器和两个倾斜反射器。 中心反射器水平地设置在线状灯阵列上方，距晶片的第一预定距离处，用于将从线状灯阵列的中心部分照射的光反射到晶片。 两侧反射器水平地设置在线状灯的上方距离晶片的第二预定距离处，其中第二预定距离小于第一预定距离，并且分别连接到中心反射器的两个相对的侧部，以反射从 线性灯阵列的侧面部分到晶片。 两个倾斜反射器分别以两个倾斜的角度连接到两个第一侧反射器中的每一个的一侧到晶片，用于将从线状灯阵列的两个端部照射的光反射到晶片。

公开(公告)号：US07579668B2

公开(公告)日：2009-08-25

申请号：US11875287

申请日：2007-10-19

Applicant: Chee-Wee Liu ,  Chun-Hung Lai ,  Meng-kun Chen ,  Wei-Shuo Ho

Inventor： Chee-Wee Liu ,  Chun-Hung Lai ,  Meng-kun Chen ,  Wei-Shuo Ho

IPC: H01L31/06 ,  H01L27/148 ,  H01L29/768 ,  H01L31/062 ,  H01L31/113

CPC classification number: H01L31/103 ,  H01L27/1446

Abstract: A method for photo-detecting and an apparatus for the same are provided. The apparatus for photo-detecting includes a first P-N diode and a second P-N diode. The first P-N diode, has a first P-N junction which has a first thickness, by which a first electrical signal is generated when irradiated by light, and the second P-N diode has a second P-N junction which has a second thickness, by which a second electrical signal is generated when irradiated by light. The second thickness is larger than the first thickness and an operation of the first electrical signal and the second electrical signal is proceeded for obtaining a third electrical signal.

Abstract translation: 提供了一种用于光电检测的方法及其装置。 用于光检测的装置包括第一P-N二极管和第二P-N二极管。 第一PN二极管具有第一PN结，其具有第一厚度，当被光照射时，第一PN信号产生第一电信号，并且第二PN二极管具有第二PN结，第二PN结具有第二厚度，第二PN 当光照射时产生信号。 第二厚度大于第一厚度，并且进行第一电信号和第二电信号的操作以获得第三电信号。

公开(公告)号：US20080217651A1

公开(公告)日：2008-09-11

申请号：US11829257

申请日：2007-07-27

Applicant: Chee-Wee Liu ,  Chu-Hsuan Lin ,  Cheng-The Yu

Inventor： Chee-Wee Liu ,  Chu-Hsuan Lin ,  Cheng-The Yu

IPC: H01L31/028 ,  H01L31/0224

CPC classification number: H01L31/113 ,  H01L31/1804 ,  Y02E10/547 ,  Y02P70/521

Abstract: A photodetector is provided. The photodetector includes a base piece; a germanium layer mounted on the base piece and including a first area and a second area; a first metal electrode mounted on the first area; an insulation layer mounted on the second area; and a second metal electrode mounted on the insulation layer.

Abstract translation: 提供光电检测器。 光检测器包括基片; 安装在所述基片上并包括第一区域和第二区域的锗层; 安装在第一区域上的第一金属电极; 安装在所述第二区域上的绝缘层; 以及安装在所述绝缘层上的第二金属电极。

公开(公告)号：US20080142908A1

公开(公告)日：2008-06-19

申请号：US11877812

申请日：2007-10-24

Applicant: Chih-Hung Tseng ,  Hsien-Ta Wu ,  Cheng-Yi Peng ,  Chee-Wee Liu

Inventor： Chih-Hung Tseng ,  Hsien-Ta Wu ,  Cheng-Yi Peng ,  Chee-Wee Liu

IPC: H01L29/78 ,  H01L21/3205

CPC classification number: H01L21/28088 ,  H01L29/4966

Abstract: A method of using an III-V semiconductor material as a gate electrode is provided. The method includes steps of providing a substrate; forming a gate dielectric layer on the substrate; and forming the III-V semiconductor material on the gate dielectric layer.

Abstract translation: 提供了使用III-V族半导体材料作为栅电极的方法。 该方法包括提供衬底的步骤; 在所述基板上形成栅介电层; 以及在栅介质层上形成III-V族半导体材料。

公开(公告)号：US07307004B2

公开(公告)日：2007-12-11

申请号：US10982375

申请日：2004-11-05

Applicant: Cheng-Ya Yu ,  Sun-Rong Jan ,  Shu-Tong Chang ,  Chee-Wee Liu

Inventor： Cheng-Ya Yu ,  Sun-Rong Jan ,  Shu-Tong Chang ,  Chee-Wee Liu

IPC: H01L21/00

CPC classification number: H01L21/7624 ,  H01L21/823807 ,  H01L29/7842 ,  H01L29/786

Abstract: A method with a mechanically strained silicon for enhancing the speeds of integrated circuits or devices is disclosed. The method with a mechanically strained silicon for enhancing the speeds of integrated circuits or devices includes the following steps: (a) providing a substrate, (b) fixing the substrate, (c) applying a stress upon the substrate, and (d) inducing a strain in one of a device and a circuit by stressing the substrate.

Abstract translation: 公开了一种具有用于增强集成电路或装置的速度的机械应变硅的方法。 具有用于增强集成电路或器件的速度的机械应变硅的方法包括以下步骤：（a）提供衬底，（b）固定衬底，（c）在衬底上施加应力，以及（d）诱导 通过施加基板在器件和电路之一中的应变。

公开(公告)号：US07091522B2

公开(公告)日：2006-08-15

申请号：US10791816

申请日：2004-03-04

Applicant: Min-Hung Lee ,  Shu Tong Chang ,  Shing Chii Lu ,  Chee-Wee Liu

Inventor： Min-Hung Lee ,  Shu Tong Chang ,  Shing Chii Lu ,  Chee-Wee Liu

IPC: H01L29/15

CPC classification number: H01L29/1054 ,  H01L29/6659

Abstract: A MOSFET structure utilizing strained silicon carbon alloy and fabrication method thereof. The MOSFET structure includes a substrate, a graded SiGe layer, a relaxed buffer layer, a strained silicon carbon alloy channel layer, a gate dielectric layer, a polysilicon gate electrode (or metal gate electrode) and a source/drain region.

Abstract translation: 利用应变硅碳合金的MOSFET结构及其制造方法。 MOSFET结构包括衬底，渐变SiGe层，松弛缓冲层，应变硅碳合金沟道层，栅介质层，多晶硅栅电极（或金属栅电极）和源/漏区。

公开(公告)号：US20050179028A1

公开(公告)日：2005-08-18

申请号：US10915362

申请日：2004-08-11

Applicant: Pang-Shiu Chen ,  Sheng-Wei Lee ,  Kao-Feng Liao ,  Lih-Juann Chen ,  Chee-Wee Liu

Inventor： Pang-Shiu Chen ,  Sheng-Wei Lee ,  Kao-Feng Liao ,  Lih-Juann Chen ,  Chee-Wee Liu

IPC: H01L21/20 ,  H01L29/06 ,  H01L29/10 ,  H01L29/165

CPC classification number: H01L29/1054 ,  H01L21/02381 ,  H01L21/02447 ,  H01L21/0245 ,  H01L21/02502 ,  H01L21/02532 ,  H01L29/165

Abstract: A construction of thin strain-relaxed SiGe layers and method for fabricating the same is provided. The construction includes a semiconductor substrate, a SiGe buffer layer formed on the semiconductor substrate, a Si(C) layer formed on the SiGe buffer layer, and an relaxed SiGe epitaxial layer formed on the Si(C) layer. The Si(C) layer is employed to change the strain-relaxed mechanism of the relaxed SiGe epitaxial layer formed on the Si(C) layer. Therefore, a thin relaxed SiGe epitaxial layer with low threading dislocation density, smooth surface is available. The fabricating time for fabricating the strain-relaxed SiGe layers is greatly reduced and the surface roughness is also improved.

Abstract translation: 提供了薄应变松弛SiGe层的结构及其制造方法。 该结构包括半导体衬底，形成在半导体衬底上的SiGe缓冲层，形成在SiGe缓冲层上的Si（C）层和形成在Si（C）层上的松弛SiGe外延层）。 Si（C）层用于改变形成在Si（C）层上的弛豫SiGe外延层的应变松弛机理。 因此，具有低穿透位错密度，光滑表面的薄弛豫SiGe外延层是可用的。 制造应变松弛SiGe层的制造时间大大降低，表面粗糙度也得到改善。

公开(公告)号：US20050023520A1

公开(公告)日：2005-02-03

申请号：US10791816

申请日：2004-03-04

Applicant: Min-Hung Lee ,  Shu Chang ,  Shing Lu ,  Chee-Wee Liu

Inventor： Min-Hung Lee ,  Shu Chang ,  Shing Lu ,  Chee-Wee Liu

IPC: H01L21/336 ,  H01L29/10 ,  H01L29/06

CPC classification number: H01L29/1054 ,  H01L29/6659

Abstract: A MOSFET structure utilizing strained silicon carbon alloy and fabrication method thereof. The MOSFET structure includes a substrate, a graded SiGe layer, a relaxed buffer layer, a strained silicon carbon alloy channel layer, a gate dielectric layer, a polysilicon gate electrode (or metal gate electrode) and a source/drain region.

Abstract translation: 利用应变硅碳合金的MOSFET结构及其制造方法。 MOSFET结构包括衬底，渐变SiGe层，松弛缓冲层，应变硅碳合金沟道层，栅介质层，多晶硅栅电极（或金属栅电极）和源/漏区。

公开(公告)号：US20140131768A1

公开(公告)日：2014-05-15

申请号：US13672971

申请日：2012-11-09

Applicant: Chun-Lin Chu ,  Shu-Han Hsu ,  Guang-Li Luo ,  Chee-Wee Liu

Inventor： Chun-Lin Chu ,  Shu-Han Hsu ,  Guang-Li Luo ,  Chee-Wee Liu

IPC: H01L29/267 ,  H01L29/12

CPC classification number: H01L29/0673 ,  B82Y10/00 ,  H01L29/32 ,  H01L29/42392 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/66439 ,  H01L29/775 ,  H01L29/78696

Abstract: A bridge structure for use in a semiconductor device includes a semiconductor substrate and a semiconductor structure layer. The semiconductor structure layer is formed on a surface of the semiconductor substrate and a lattice difference is formed between the semiconductor structure layer and the semiconductor substrate. The semiconductor structure layer includes at least a first block, at least a second block and at least a third block, wherein the first block and the third block are bonded on the surface of the semiconductor substrate, the second block is floated over the semiconductor substrate and connected with the first block and the third block.

Abstract translation: 用于半导体器件的桥结构包括半导体衬底和半导体结构层。 半导体结构层形成在半导体衬底的表面上，并且在半导体结构层和半导体衬底之间形成晶格差。 半导体结构层至少包括第一块，至少第二块和至少第三块，其中第一块和第三块结合在半导体衬底的表面上，第二块浮在半导体衬底上 并与第一块和第三块连接。

公开(公告)号：US20110284074A1

公开(公告)日：2011-11-24

申请号：US12891721

申请日：2010-09-27

Applicant: Chee-Wee Liu ,  Wei-Shuo Ho ,  Yen-Yu Chen ,  Chun-Yuan Ku ,  Chien-Jen Chen ,  Han-Tu Lin ,  Shuo-Wei Liang

Inventor： Chee-Wee Liu ,  Wei-Shuo Ho ,  Yen-Yu Chen ,  Chun-Yuan Ku ,  Chien-Jen Chen ,  Han-Tu Lin ,  Shuo-Wei Liang

IPC: H01L31/0376

CPC classification number: H01L31/0747 ,  Y02E10/50

Abstract: A photovoltaic cell includes a first type doped mono-crystalline silicon substrate, an intrinsic amorphous silicon layer, a second type doped amorphous silicon layer, a first type doped crystalline Ge-containing layer, and a pair of electrodes. The first type doped mono-crystalline silicon substrate has a front surface and a rear surface. The intrinsic amorphous silicon layer is disposed on the front surface. The second type doped amorphous silicon layer is disposed on the intrinsic amorphous silicon layer. The first type doped crystalline Ge-containing layer is disposed on the rear surface. The pair of electrodes are electrically connected to the second type doped amorphous silicon layer and first type doped crystalline Ge-containing layer, respectively.

Abstract translation: 光伏电池包括第一掺杂单晶硅衬底，本征非晶硅层，第二掺杂非晶硅层，第一掺杂晶体Ge含量层和一对电极。 第一种掺杂单晶硅衬底具有前表面和后表面。 本征非晶硅层设置在前表面上。 第二类掺杂非晶硅层设置在本征非晶硅层上。 第一类型的掺杂结晶Ge含量层设置在后表面上。 该对电极分别电连接到第二类掺杂非晶硅层和第一掺杂结晶Ge含量层。