公开(公告)号：US08643147B2

公开(公告)日：2014-02-04

申请号：US11933931

申请日：2007-11-01

申请人： Shin-Puu Jeng ,  Shih-Hsun Hsu ,  Shang-Yun Hou ,  Hao-Yi Tsai ,  Chen-Hua Yu

发明人： Shin-Puu Jeng ,  Shih-Hsun Hsu ,  Shang-Yun Hou ,  Hao-Yi Tsai ,  Chen-Hua Yu

IPC分类号： H01L23/544

CPC分类号： H01L23/562 ,  H01L23/585 ,  H01L2924/0002 ,  H01L2924/00

摘要： An integrated circuit structure includes a lower dielectric layer; an upper dielectric layer over the lower dielectric layer; and a seal ring. The seal ring includes an upper metal line in the upper dielectric layer; a continuous via bar underlying and abutting the upper metal line, wherein the continuous via bar has a width greater than about 70 percent of a width of the upper metal line; a lower metal line in the lower dielectric layer; and a via bar underlying and abutting the lower metal line. The via bar has a width substantially less than a half of a width of the lower metal line.

摘要翻译： 集成电路结构包括下介电层; 在下介电层上的上电介质层; 和密封环。 密封环包括在上介电层中的上金属线; 连续的通孔条，其下面并邻接上部金属线，其中所述连续通孔条具有大于所述上部金属线宽度的约70％的宽度; 下介电层中的下金属线; 以及位于下金属线下方并邻接的通孔条。 通孔棒具有基本上小于下金属线宽度的一半的宽度。

公开(公告)号：US08125052B2

公开(公告)日：2012-02-28

申请号：US11842821

申请日：2007-08-21

申请人： Shin-Puu Jeng ,  Shih-Hsun Hsu ,  Shang-Yun Hou ,  Hao-Yi Tsai ,  Chen-Hua Yu

发明人： Shin-Puu Jeng ,  Shih-Hsun Hsu ,  Shang-Yun Hou ,  Hao-Yi Tsai ,  Chen-Hua Yu

IPC分类号： H01L23/00

CPC分类号： H01L23/585 ,  H01L2924/0002 ,  H01L2924/00

摘要： An integrated circuit structure includes a semiconductor chip comprising a plurality of dielectric layers, wherein the plurality of dielectric layers includes a top dielectric layer; and a first seal ring adjacent edges of the semiconductor chip. The integrated circuit structure further includes a first passivation layer over a top dielectric layer; and a trench extending from a top surface of the first passivation layer into the first passivation layer, wherein the trench substantially forms a ring. Each side of the ring is adjacent to a respective edge of the semiconductor chip. At least one of the plurality of vias has a width greater than about 70 percent of a width of a respective overlying metal line in the plurality of metal lines.

摘要翻译： 集成电路结构包括包括多个电介质层的半导体芯片，其中所述多个电介质层包括顶部电介质层; 以及与所述半导体芯片的边缘相邻的第一密封环。 集成电路结构还包括在顶部介电层上的第一钝化层; 以及从所述第一钝化层的顶表面延伸到所述第一钝化层中的沟槽，其中所述沟槽基本上形成环。 环的每一侧与半导体芯片的相应边缘相邻。 所述多个通孔中的至少一个具有大于所述多个金属线中相应的上覆金属线的宽度的约70％的宽度。

公开(公告)号：US20090115024A1

公开(公告)日：2009-05-07

申请号：US11933931

申请日：2007-11-01

申请人： Shin-Puu Jeng ,  Shih-Hsun Hsu ,  Shang-Yun Hou ,  Hao-Yi Tsai ,  Chen-Hua Yu

发明人： Shin-Puu Jeng ,  Shih-Hsun Hsu ,  Shang-Yun Hou ,  Hao-Yi Tsai ,  Chen-Hua Yu

IPC分类号： H01L23/52

CPC分类号： H01L23/562 ,  H01L23/585 ,  H01L2924/0002 ,  H01L2924/00

摘要： An integrated circuit structure includes a lower dielectric layer; an upper dielectric layer over the lower dielectric layer; and a seal ring. The seal ring includes an upper metal line in the upper dielectric layer; a continuous via bar underlying and abutting the upper metal line, wherein the continuous via bar has a width greater than about 70 percent of a width of the upper metal line; a lower metal line in the lower dielectric layer; and a via bar underlying and abutting the lower metal line. The via bar has a width substantially less than a half of a width of the lower metal line.

摘要翻译： 集成电路结构包括下介电层; 在下介电层上的上电介质层; 和密封环。 密封环包括在上介电层中的上金属线; 连续的通孔条，其下面并邻接上部金属线，其中所述连续通孔条具有大于所述上部金属线宽度的约70％的宽度; 下介电层中的下金属线; 以及位于下金属线下方并邻接的通孔条。 通孔棒具有基本上小于下金属线宽度的一半的宽度。

公开(公告)号：US20080283969A1

公开(公告)日：2008-11-20

申请号：US11842821

申请日：2007-08-21

申请人： Shin-Puu Jeng ,  Shih-Hsun Hsu ,  Shang-Yun Hou ,  Hao-Yi Tsai ,  Chen-Hua Yu

发明人： Shin-Puu Jeng ,  Shih-Hsun Hsu ,  Shang-Yun Hou ,  Hao-Yi Tsai ,  Chen-Hua Yu

IPC分类号： H01L23/00

CPC分类号： H01L23/585 ,  H01L2924/0002 ,  H01L2924/00

摘要： An integrated circuit structure includes a semiconductor chip comprising a plurality of dielectric layers, wherein the plurality of dielectric layers includes a top dielectric layer; and a first seal ring adjacent edges of the semiconductor chip. The integrated circuit structure further includes a first passivation layer over a top dielectric layer; and a trench extending from a top surface of the first passivation layer into the first passivation layer, wherein the trench substantially forms a ring. Each side of the ring is adjacent to a respective edge of the semiconductor chip. At least one of the plurality of vias has a width greater than about 70 percent of a width of a respective overlying metal line in the plurality of metal lines.

摘要翻译： 集成电路结构包括包括多个电介质层的半导体芯片，其中所述多个电介质层包括顶部电介质层; 以及与所述半导体芯片的边缘相邻的第一密封环。 集成电路结构还包括在顶部介电层上的第一钝化层; 以及从所述第一钝化层的顶表面延伸到所述第一钝化层中的沟槽，其中所述沟槽基本上形成环。 环的每一侧与半导体芯片的相应边缘相邻。 所述多个通孔中的至少一个具有大于所述多个金属线中相应的上覆金属线的宽度的约70％的宽度。

公开(公告)号：US08227916B2

公开(公告)日：2012-07-24

申请号：US12757440

申请日：2010-04-09

申请人： Hsiu-Ping Wei ,  Shin-Puu Jeng ,  Hao-Yi Tsai ,  Hsien-Wei Chen ,  Yu-Wen Liu ,  Ying-Ju Chen ,  Tzuan-Horng Liu

发明人： Hsiu-Ping Wei ,  Shin-Puu Jeng ,  Hao-Yi Tsai ,  Hsien-Wei Chen ,  Yu-Wen Liu ,  Ying-Ju Chen ,  Tzuan-Horng Liu

IPC分类号： H01L23/498 ,  H01L21/3205

CPC分类号： H01L21/76801 ,  H01L23/3192 ,  H01L23/522 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/02166 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/03462 ,  H01L2224/03464 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05008 ,  H01L2224/05022 ,  H01L2224/05096 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05572 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05666 ,  H01L2224/05671 ,  H01L2224/1145 ,  H01L2224/11452 ,  H01L2224/11462 ,  H01L2224/11464 ,  H01L2224/13116 ,  H01L2224/13147 ,  H01L2224/16 ,  H01L2924/0002 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/00014 ,  H01L2224/05552 ,  H01L2924/00

摘要： A semiconductor package structure is provided. The structure includes a semiconductor chip having a plurality of interconnect layers formed thereover. A first passivation layer is formed over the plurality of interconnect layers. A stress buffer layer is formed over the first passivation layer. A bonding pad is formed over the stress buffer layer. A second passivation layer is formed over a portion of the bonding pad, the second passivation having at least one opening therein exposing a portion of the bonding pad.

摘要翻译： 提供半导体封装结构。 该结构包括其上形成有多个互连层的半导体芯片。 在多个互连层上形成第一钝化层。 在第一钝化层上形成应力缓冲层。 在应力缓冲层上形成接合焊盘。 在接合焊盘的一部分上形成第二钝化层，第二钝化层具有至少一个开口，露出焊接区的一部分。

公开(公告)号：US20110031618A1

公开(公告)日：2011-02-10

申请号：US12813763

申请日：2010-06-11

申请人： Chen-Hua Yu ,  Shin-Puu Jeng ,  Hao-Yi Tsai ,  Hsien-Wei Chen

发明人： Chen-Hua Yu ,  Shin-Puu Jeng ,  Hao-Yi Tsai ,  Hsien-Wei Chen

IPC分类号： H01L23/498

CPC分类号： H01L24/11 ,  H01L23/3192 ,  H01L2224/0401 ,  H01L2224/05006 ,  H01L2224/05124 ,  H01L2224/05139 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05184 ,  H01L2224/05552 ,  H01L2224/05572 ,  H01L2224/05655 ,  H01L2224/13006 ,  H01L2224/13099 ,  H01L2224/16225 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/3511 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/013

摘要： An integrated circuit structure includes a semiconductor substrate, and an active device formed at a front surface of the semiconductor substrate. A bond pad is over the front surface of the semiconductor substrate. The bond pad has a first dimension in a first direction parallel to the front surface of the semiconductor substrate. A bump ball is over the bond pad, wherein the bump ball has a diameter in the first direction, and wherein an enclosure of the first dimension and the diameter is greater than about −1 μm.

摘要翻译： 集成电路结构包括半导体衬底和形成在半导体衬底的前表面的有源器件。 接合焊盘在半导体衬底的前表面之上。 接合焊盘在与半导体基板的前表面平行的第一方向上具有第一尺寸。 凸块球在接合垫上方，其中凸块球具有在第一方向上的直径，并且其中第一尺寸和直径的外壳大于约-1μm。

公开(公告)号：US08203209B2

公开(公告)日：2012-06-19

申请号：US12813763

申请日：2010-06-11

申请人： Chen-Hua Yu ,  Shin-Puu Jeng ,  Hao-Yi Tsai ,  Hsien-Wei Chen

发明人： Chen-Hua Yu ,  Shin-Puu Jeng ,  Hao-Yi Tsai ,  Hsien-Wei Chen

IPC分类号： H01L23/498

CPC分类号： H01L24/11 ,  H01L23/3192 ,  H01L2224/0401 ,  H01L2224/05006 ,  H01L2224/05124 ,  H01L2224/05139 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05184 ,  H01L2224/05552 ,  H01L2224/05572 ,  H01L2224/05655 ,  H01L2224/13006 ,  H01L2224/13099 ,  H01L2224/16225 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/3511 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/013

摘要： An integrated circuit structure includes a semiconductor substrate, and an active device formed at a front surface of the semiconductor substrate. A bond pad is over the front surface of the semiconductor substrate. The bond pad has a first dimension in a first direction parallel to the front surface of the semiconductor substrate. A bump ball is over the bond pad, wherein the bump ball has a diameter in the first direction, and wherein an enclosure of the first dimension and the diameter is greater than about −1 μm.

摘要翻译： 集成电路结构包括半导体衬底和形成在半导体衬底的前表面的有源器件。 接合焊盘在半导体衬底的前表面之上。 接合焊盘在与半导体基板的前表面平行的第一方向上具有第一尺寸。 凸块球在接合垫上方，其中凸块球具有在第一方向上的直径，并且其中第一尺寸和直径的外壳大于约-1μm。

公开(公告)号：US20090011539A1

公开(公告)日：2009-01-08

申请号：US11971072

申请日：2008-01-08

申请人： Shin-Puu Jeng ,  Shang-Yun Hou ,  Hao-Yi Tsai ,  Anbiarshy N.F. Wu

发明人： Shin-Puu Jeng ,  Shang-Yun Hou ,  Hao-Yi Tsai ,  Anbiarshy N.F. Wu

IPC分类号： H01L21/00

CPC分类号： H01L22/34 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for forming an integrated circuit structure includes forming a test wafer. The step of forming the test wafer includes providing a first semiconductor substrate; and forming a first plurality of unit blocks over the first semiconductor substrate. Each of the first plurality of unit blocks includes a plurality of connection block cells arranged as an array. Each of the connection block cells includes two connection blocks, and a metal line connecting the two connection blocks. The method further includes forming a plurality of unit block boundary lines separating the first plurality of unit blocks from each other; and forming a first plurality of metal lines connecting a portion of the first plurality of unit blocks.

摘要翻译： 一种用于形成集成电路结构的方法包括形成测试晶片。 形成测试晶片的步骤包括提供第一半导体衬底; 以及在所述第一半导体衬底上形成第一多个单元块。 第一多个单元块中的每一个包括被排列成阵列的多个连接块单元。 每个连接块单元包括两个连接块和连接两个连接块的金属线。 该方法还包括形成将第一多个单元块彼此分开的多个单位块边界线; 以及形成连接所述第一多个单元块的一部分的第一多个金属线。

公开(公告)号：US20070132059A1

公开(公告)日：2007-06-14

申请号：US11299999

申请日：2005-12-12

申请人： Hao-Yi Tsai ,  Chao-Hsiang Yang ,  Shang-Yun Hou ,  Chia-Lun Tsai ,  Shin-Puu Jeng

发明人： Hao-Yi Tsai ,  Chao-Hsiang Yang ,  Shang-Yun Hou ,  Chia-Lun Tsai ,  Shin-Puu Jeng

IPC分类号： H01L29/00

CPC分类号： H01L23/5258 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor structure having an efficient thermal path and a method for forming the same are provided. The semiconductor structure includes a protection ring over a semiconductor substrate and substantially encloses a laser fuse structure. The laser fuse structure includes a laser fuse and a connection structure connecting the fuse to integrated circuits. The protection ring is thermally coupled to the semiconductor substrate by contacts. The semiconductor structure further includes a metal plate conducting heat generated by a laser beam to the protection ring.

摘要翻译： 提供了具有有效的热路径的半导体结构及其形成方法。 半导体结构包括半导体衬底上的保护环，并且基本上包围激光熔丝结构。 激光熔丝结构包括激光熔丝和将熔丝连接到集成电路的连接结构。 保护环通过触点热耦合到半导体衬底。 半导体结构还包括将由激光束产生的热量传导到保护环的金属板。

公开(公告)号：US08519512B2

公开(公告)日：2013-08-27

申请号：US11525575

申请日：2006-09-22

申请人： Hao-Yi Tsai ,  Chia-Lun Tsai ,  Shang-Yun Hou ,  Shin-Puu Jeng ,  Shih-Hsun Hsu ,  Wei-Ti Hsu ,  Lin-Ko Feng ,  Chun-Jen Chen

发明人： Hao-Yi Tsai ,  Chia-Lun Tsai ,  Shang-Yun Hou ,  Shin-Puu Jeng ,  Shih-Hsun Hsu ,  Wei-Ti Hsu ,  Lin-Ko Feng ,  Chun-Jen Chen

IPC分类号： H01L23/544

CPC分类号： H01L21/78 ,  H01L21/782 ,  H01L21/784 ,  H01L21/786 ,  H01L22/10 ,  H01L22/34 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor wafer structure includes a plurality of dies, a first scribe line extending along a first direction, a second scribe line extending along a second direction and intersecting the first scribe line, wherein the first and the second scribe lines have an intersection region. A test line is formed in the scribe line, wherein the test line crosses the intersection region. Test pads are formed in the test line and only outside a free region defined substantially in the intersection region.