公开(公告)号：US08362558B2

公开(公告)日：2013-01-29

申请号：US13100449

申请日：2011-05-04

申请人： Hsueh-I Huang ,  Chien-Wen Chu ,  Cheng-Chi Lin ,  Shih-Chin Lien ,  Chin-Pen Yeh ,  Shyi-Yuan Wu

发明人： Hsueh-I Huang ,  Chien-Wen Chu ,  Cheng-Chi Lin ,  Shih-Chin Lien ,  Chin-Pen Yeh ,  Shyi-Yuan Wu

IPC分类号： H01L29/02

CPC分类号： H01L29/0847 ,  H01L29/42368 ,  H01L29/66659 ,  H01L29/7835

摘要： A lateral-double diffused MOS device is provided. The device includes: a first well having a first conductive type and a second well having a second conductive type disposed in a substrate and adjacent to each other; a drain and a source regions having the first conductive type disposed in the first and the second wells, respectively; a field oxide layer (FOX) disposed on the first well between the source and the drain regions; a gate conductive layer disposed over the second well between the source and the drain regions extending to the FOX; a gate dielectric layer between the substrate and the gate conductive layer; a doped region having the first conductive type in the first well below a portion of the gate conductive layer and the FOX connecting to the drain region. A channel region is defined in the second well between the doped region and the source region.

摘要翻译： 提供了横向双扩散MOS器件。 该装置包括：具有第一导电类型的第一阱和具有布置在衬底中并且彼此相邻的第二导电类型的第二阱; 漏极和分别设置在第一和第二阱中的具有第一导电类型的源极区域; 设置在源极和漏极区域之间的第一阱上的场氧化物层（FOX）; 设置在延伸到FOX的源极和漏极区域之间的第二阱上的栅极导电层; 在所述基板和所述栅极导电层之间的栅极介电层; 在栅极导电层的一部分下方的第一阱中具有第一导电类型的掺杂区域和连接到漏极区域的FOX。 在掺杂区域和源极区域之间的第二阱中限定沟道区域。

公开(公告)号：US20110266601A1

公开(公告)日：2011-11-03

申请号：US13180236

申请日：2011-07-11

申请人： Cheng-Chi Lin ,  Shih-Chin Lien ,  Chin-Pen Yeh ,  Shyi-Yuan Wu

发明人： Cheng-Chi Lin ,  Shih-Chin Lien ,  Chin-Pen Yeh ,  Shyi-Yuan Wu

IPC分类号： H01L29/772

CPC分类号： H01L29/6659 ,  H01L27/11558 ,  H01L29/1083 ,  H01L29/66825 ,  H01L29/7833 ,  H01L29/788

摘要： A semiconductor device has a gate multiple doping regions on both sides of the gate. The gate can be shared by a transistor and a capacitor.

摘要翻译： 半导体器件在栅极的两侧具有栅极多个掺杂区域。 栅极可以由晶体管和电容器共享。

公开(公告)号：US20090256184A1

公开(公告)日：2009-10-15

申请号：US12102637

申请日：2008-04-14

申请人： Cheng-Chi Lin ,  Shih-Chin Lien ,  Chin-Pen Yeh ,  Shyi-Yuan Wu

发明人： Cheng-Chi Lin ,  Shih-Chin Lien ,  Chin-Pen Yeh ,  Shyi-Yuan Wu

IPC分类号： H01L27/105 ,  H01L21/8239

CPC分类号： H01L29/6659 ,  H01L27/11558 ,  H01L29/1083 ,  H01L29/66825 ,  H01L29/7833 ,  H01L29/788

摘要： A nonvolatile memory integrated circuit has a semiconductor substrate and a nonvolatile memory device on the semiconductor substrate. The device has a transistor and a capacitor on the semiconductor substrate, and a shared floating gate connecting the gate regions of the transistor and the capacitor. The transistor has at least a doping region defining the source and drain regions, as well as three other doping regions overlapping the source and drain regions. Also disclosed are a nonvolatile memory circuit with multiple such nonvolatile memory device, and methods for making the nonvolatile memory circuit with one or more such nonvolatile memory devices.

摘要翻译： 非易失性存储器集成电路在半导体衬底上具有半导体衬底和非易失性存储器件。 该器件在半导体衬底上具有晶体管和电容器，以及连接晶体管的栅极区域和电容器的共用浮置栅极。 晶体管至少具有限定源极和漏极区域的掺杂区域以及与源极和漏极区域重叠的三个其它掺杂区域。 还公开了具有多个这种非易失性存储器件的非易失性存储器电路以及用于使非易失性存储器电路具有一个或多个这种非易失性存储器件的方法

公开(公告)号：US08921933B2

公开(公告)日：2014-12-30

申请号：US13111018

申请日：2011-05-19

申请人： Shyi-Yuan Wu ,  Wing-Chor Chan ,  Shih-Chin Lien ,  Cheng-Chi Lin

发明人： Shyi-Yuan Wu ,  Wing-Chor Chan ,  Shih-Chin Lien ,  Cheng-Chi Lin

IPC分类号： H01L29/66 ,  H01L29/78 ,  H01L29/739 ,  H01L29/06 ,  H01L29/08 ,  H01L29/423

CPC分类号： H01L29/7824 ,  H01L29/0634 ,  H01L29/0653 ,  H01L29/0692 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/42368 ,  H01L29/7397 ,  H01L29/7809 ,  H01L29/7813 ,  H01L29/7816 ,  H01L29/7817 ,  H01L29/7825 ,  H01L29/7831 ,  H01L29/7835

摘要： A semiconductor structure and a method for operating the same are provided. The semiconductor structure includes a substrate, a first doped region, a second doped region, a third doped region, a first trench structure and a second gate structure. The first doped region is in the substrate. The first doped region has a first conductivity type. The second doped region is in the first doped region. The second doped region has a second conductivity type opposite to the first conductivity type. The third doped region having the first conductivity type is in the second doped region. The first trench structure has a first gate structure. The first gate structure and the second gate structure are respectively on different sides of the second doped region.

摘要翻译： 提供半导体结构及其操作方法。 半导体结构包括衬底，第一掺杂区，第二掺杂区，第三掺杂区，第一沟槽结构和第二栅结构。 第一掺杂区域在衬底中。 第一掺杂区具有第一导电类型。 第二掺杂区域在第一掺杂区域中。 第二掺杂区具有与第一导电类型相反的第二导电类型。 具有第一导电类型的第三掺杂区域在第二掺杂区域中。 第一沟槽结构具有第一栅极结构。 第一栅极结构和第二栅极结构分别位于第二掺杂区域的不同侧。

公开(公告)号：US20140061721A1

公开(公告)日：2014-03-06

申请号：US13596745

申请日：2012-08-28

申请人： Ching-Lin Chan ,  Shyi-Yuan Wu ,  Cheng-Chi Lin ,  Shih-Chin Lien

发明人： Ching-Lin Chan ,  Shyi-Yuan Wu ,  Cheng-Chi Lin ,  Shih-Chin Lien

IPC分类号： H01L29/78 ,  H01L29/739 ,  H01L21/331 ,  H01L21/336

CPC分类号： H01L29/6609 ,  H01L29/0634 ,  H01L29/0878 ,  H01L29/1087 ,  H01L29/42368 ,  H01L29/66325 ,  H01L29/66689 ,  H01L29/7393 ,  H01L29/7816 ,  H01L29/861

摘要： An improved MOS device is provided whereby the p-top layer is defined by a series of discretely placed p type top diffusion regions. The invention also provides methods for fabricating the MOS device of the invention.

摘要翻译： 提供了一种改进的MOS器件，由此p顶层由一系列离散地放置的p型顶部扩散区限定。 本发明还提供了制造本发明的MOS器件的方法。

公开(公告)号：US08017486B2

公开(公告)日：2011-09-13

申请号：US11767205

申请日：2007-06-22

申请人： Hsueh-I Huang ,  Chien-Wen Chu ,  Cheng-Chi Lin ,  Shih-Chin Lien ,  Chin-Pen Yeh ,  Shyi-Yuan Wu

发明人： Hsueh-I Huang ,  Chien-Wen Chu ,  Cheng-Chi Lin ,  Shih-Chin Lien ,  Chin-Pen Yeh ,  Shyi-Yuan Wu

IPC分类号： H01L21/336

CPC分类号： H01L29/0847 ,  H01L29/42368 ,  H01L29/66659 ,  H01L29/7835

摘要： A lateral-double diffused MOS device is provided. The device includes: a first well having a first conductive type and a second well having a second conductive type disposed in a substrate and adjacent to each other; a drain and a source regions having the first conductive type disposed in the first and the second wells, respectively; a field oxide layer (FOX) disposed on the first well between the source and the drain regions; a gate conductive layer disposed over the second well between the source and the drain regions extending to the FOX; a gate dielectric layer between the substrate and the gate conductive layer; a doped region having the first conductive type in the first well below a portion of the gate conductive layer and the FOX connecting to the drain region. A channel region is defined in the second well between the doped region and the source region.

摘要翻译： 提供了横向双扩散MOS器件。 该装置包括：具有第一导电类型的第一阱和具有布置在衬底中并且彼此相邻的第二导电类型的第二阱; 漏极和分别设置在第一和第二阱中的具有第一导电类型的源极区域; 设置在源极和漏极区域之间的第一阱上的场氧化物层（FOX）; 设置在延伸到FOX的源极和漏极区域之间的第二阱上的栅极导电层; 在所述基板和所述栅极导电层之间的栅极介电层; 在栅极导电层的一部分下方的第一阱中具有第一导电类型的掺杂区域和连接到漏极区域的FOX。 在掺杂区域和源极区域之间的第二阱中限定沟道区域。

公开(公告)号：US20110121373A1

公开(公告)日：2011-05-26

申请号：US12876711

申请日：2010-09-07

申请人： Cheng-Chi Lin ,  Shih-Chin Lien ,  Shyi-Yuan Wu ,  Chin-Pen Yeh

发明人： Cheng-Chi Lin ,  Shih-Chin Lien ,  Shyi-Yuan Wu ,  Chin-Pen Yeh

IPC分类号： H01L27/06

CPC分类号： H01L27/0629 ,  H01L27/11558 ,  H01L29/66825 ,  H01L29/7881

摘要： A semiconductor memory device includes a substrate of a first impurity type, a first well region of a second impurity type in the substrate, the second impurity type being different from the first impurity type, a second well region of the first impurity type in the substrate, a patterned first dielectric layer on the substrate extending over the first and second well regions, a patterned first gate structure on the patterned first dielectric layer, a patterned second dielectric layer on the patterned first gate structure, and a patterned second gate structure on the patterned second dielectric layer. The patterned first gate structure may include a first section extending in a first direction and a second section extending in a second direction orthogonal to the first section, wherein the first section and the second section intersects each other in a cross pattern. The patterned second gate structure may include at least one of a first section extending in the first direction over the first section of the patterned first gate structure or a second section extending in the second direction over the second section of the patterned first gate structure.

摘要翻译： 半导体存储器件包括：第一杂质型衬底，衬底中第二杂质类型的第一阱区，第二杂质型不同于第一杂质型;衬底中第一杂质型第二阱区; 在衬底上的图案化的第一介电层延伸在第一和第二阱区上，图案化的第一介电层上的图案化的第一栅极结构，图案化的第一栅极结构上的图案化的第二介电层，以及图案化的第二栅极结构 图案化的第二介电层。 图案化的第一栅极结构可以包括沿第一方向延伸的第一部分和在与第一部分正交的第二方向延伸的第二部分，其中第一部分和第二部分以交叉图案彼此相交。 图案化的第二栅极结构可以包括在图案化的第一栅极结构的第一部分上的第一方向上延伸的第一部分或者在图案化的第一栅极结构的第二部分上沿第二方向延伸的第二部分中的至少一个。

公开(公告)号：US20080315308A1

公开(公告)日：2008-12-25

申请号：US11767205

申请日：2007-06-22

申请人： Hsueh-I Huang ,  Chien-Wen Chu ,  Cheng-Chi Lin ,  Shih-Chin Lien ,  Chin-Pen Yeh ,  Shyi-Yuan Wu

发明人： Hsueh-I Huang ,  Chien-Wen Chu ,  Cheng-Chi Lin ,  Shih-Chin Lien ,  Chin-Pen Yeh ,  Shyi-Yuan Wu

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/0847 ,  H01L29/42368 ,  H01L29/66659 ,  H01L29/7835

摘要： A lateral-double diffused MOS device is provided. The device includes: a first well having a first conductive type and a second well having a second conductive type disposed in a substrate and adjacent to each other; a drain and a source regions having the first conductive type disposed in the first and the second wells, respectively; a field oxide layer (FOX) disposed on the first well between the source and the drain regions; a gate conductive layer disposed over the second well between the source and the drain regions extending to the FOX; a gate dielectric layer between the substrate and the gate conductive layer; a doped region having the first conductive type in the first well below a portion of the gate conductive layer and the FOX connecting to the drain region. A channel region is defined in the second well between the doped region and the source region.

摘要翻译： 提供了横向双扩散MOS器件。 该装置包括：具有第一导电类型的第一阱和具有布置在衬底中并且彼此相邻的第二导电类型的第二阱; 漏极和分别设置在第一和第二阱中的具有第一导电类型的源极区域; 设置在源极和漏极区域之间的第一阱上的场氧化物层（FOX）; 设置在延伸到FOX的源极和漏极区域之间的第二阱上的栅极导电层; 在所述基板和所述栅极导电层之间的栅极介电层; 在栅极导电层的一部分下方的第一阱中具有第一导电类型的掺杂区域和连接到漏极区域的FOX。 在掺杂区域和源极区域之间的第二阱中限定沟道区域。

公开(公告)号：US08872222B2

公开(公告)日：2014-10-28

申请号：US13405001

申请日：2012-02-24

申请人： Ching-Lin Chan ,  Chen-Yuan Lin ,  Cheng-Chi Lin ,  Shih-Chin Lien

发明人： Ching-Lin Chan ,  Chen-Yuan Lin ,  Cheng-Chi Lin ,  Shih-Chin Lien

IPC分类号： H01L29/739 ,  H01L21/331

CPC分类号： H01L21/22 ,  H01L29/0634 ,  H01L29/0696 ,  H01L29/1087 ,  H01L29/42368 ,  H01L29/66325 ,  H01L29/66674 ,  H01L29/66689 ,  H01L29/7393 ,  H01L29/7816 ,  H01L29/861

摘要： A semiconductor structure and a method for forming the same are provided. The semiconductor structure comprises a first doped region, a second doped region, a doped strip and a top doped region. The first doped region has a first type conductivity. The second doped region is formed in the first doped region and has a second type conductivity opposite to the first type conductivity. The doped strip is formed in the first doped region and has the second type conductivity. The top doped region is formed in the doped strip and has the first type conductivity. The top doped region has a first sidewall and a second sidewall opposite to the first sidewall. The doped strip is extended beyond the first sidewall or the second sidewall.

摘要翻译： 提供半导体结构及其形成方法。 半导体结构包括第一掺杂区，第二掺杂区，掺杂条和顶掺杂区。 第一掺杂区域具有第一类型的导电性。 第二掺杂区域形成在第一掺杂区域中并且具有与第一类型导电性相反的第二类型导电性。 掺杂条形成在第一掺杂区中，具有第二类型的导电性。 顶部掺杂区形成在掺杂条中，具有第一类型的导电性。 顶部掺杂区域具有与第一侧壁相对的第一侧壁和第二侧壁。 掺杂的带延伸超过第一侧壁或第二侧壁。

公开(公告)号：US20120292740A1

公开(公告)日：2012-11-22

申请号：US13111563

申请日：2011-05-19

申请人： Chen-Yuan Lin ,  Cheng-Chi Lin ,  Shih-Chin Lien ,  Chin-Pen Yeh

发明人： Chen-Yuan Lin ,  Cheng-Chi Lin ,  Shih-Chin Lien ,  Chin-Pen Yeh

IPC分类号： H01L29/02 ,  H01L21/02

CPC分类号： H01L28/20 ,  H01L27/0676 ,  H01L27/0802 ,  H01L29/0692 ,  H01L29/8605

摘要： A semiconductor device comprises a semiconductor substrate, a lateral semiconductor diode, a field insulation structure, and a polysilicon resistor. The diode is formed in a surface region of the semiconductor substrate, and includes a cathode electrode and an anode electrode. The field insulation structure is disposed between the cathode and anode electrodes. The polysilicon resistor is formed over the field insulation structure, and between the cathode and anode electrodes. The polysilicon resistor is electrically connected to the cathode electrode, and electrically insulated from the anode electrode.

摘要翻译： 半导体器件包括半导体衬底，横向半导体二极管，场绝缘结构和多晶硅电阻器。 二极管形成在半导体衬底的表面区域中，并且包括阴极电极和阳极电极。 场绝缘结构设置在阴极和阳极之间。 多晶硅电阻器形成在场绝缘结构之上，并且在阴极和阳极之间。 多晶硅电阻器电连接到阴极电极，并与阳极电极电绝缘。