公开(公告)号：US06768164B2

公开(公告)日：2004-07-27

申请号：US10725052

申请日：2003-12-01

Applicant: Chi-Hui Lin ,  Chung-Lin Huang

Inventor： Chi-Hui Lin ,  Chung-Lin Huang

IPC: H01L29788

CPC classification number: H01L27/11521 ,  H01L27/115 ,  H01L29/42336 ,  H01L29/66825 ,  H01L29/7883

Abstract: A stacked gate flash memory device and method of fabricating the same. A cell of the stacked gate flash memory device in accordance with the invention is disposed in a cell trench within a substrate and source and drain regions are formed in the same substrate side of the adjacent isolation trenches. Thus, the stacked gate flash memory device of the invention can achieve high integration of memory cells.

公开(公告)号：US06734686B2

公开(公告)日：2004-05-11

申请号：US10118778

申请日：2002-04-08

Applicant: Chi-Hui Lin ,  Cheng-Jye Chu ,  Pai-Mou Lee ,  Goang-Cheng Chang

Inventor： Chi-Hui Lin ,  Cheng-Jye Chu ,  Pai-Mou Lee ,  Goang-Cheng Chang

IPC: G01R2726

CPC classification number: G01F23/268 ,  G01F23/263 ,  G01F23/266 ,  G01N27/226

Abstract: This invention relates to a method for detecting quantity variation of high purity liquid chemicals by way of detecting capacitance variation to determine the liquid level of liquid chemicals. Meanwhile, the ratio of the area of the smallest electrode of the capacitor to the distance between the electrodes is adjusted to magnify the capacitance so that a very small variation can be observed clearly. This invention also discloses a device to carry out this method.

Abstract translation: 本发明涉及一种用于通过检测电容变化来检测高纯度液体化学品的量变化以确定液体化学品的液位的方法。 同时，电容器的最小电极的面积与电极之间的距离的比率被调节以放大电容，使得可以清楚地观察到非常小的变化。 本发明还公开了一种执行该方法的装置。

公开(公告)号：US06642116B2

公开(公告)日：2003-11-04

申请号：US10191108

申请日：2002-07-08

Applicant: Chi-Hui Lin

Inventor： Chi-Hui Lin

IPC: H01L21336

CPC classification number: H01L29/42324 ,  H01L21/28273

Abstract: A method of fabricating flash memory cell is described. The method includes the steps of providing a semiconductor substrate; forming a first gate insulating layer; forming a first conductive layer; forming a buffer layer; removing portions of the buffer layer to farm a floating gate insulating layer; forming a second conductive layer; removing portions of the first conductive layer and the second conductive layer, such that the second conductive layer forms conductive spacers having conductive tips situated at the tips, and the floating gate insulating layer, the floating gate and the first gate insulating layer are combined as a floating gate region; forming a second insulating layer; forming a third conductive layer; removing portions of the third conductive layer and the second insulating layer to form a control gate, a second gate insulating layer, a first opening and a second opening; forming a source region on the substrate; forming spacers; and forming a drain region on the substrate.

Abstract translation: 描述了一种制造闪存单元的方法。 该方法包括提供半导体衬底的步骤; 形成第一栅极绝缘层; 形成第一导电层; 形成缓冲层; 去除所述缓冲层的部分以形成浮栅绝缘层; 形成第二导电层; 去除所述第一导电层和所述第二导电层的部分，使得所述第二导电层形成具有位于所述尖端处的导电尖端的导电间隔物，并且所述浮栅绝缘层，所述浮栅和所述第一栅极绝缘层被组合为 浮动栅区; 形成第二绝缘层; 形成第三导电层; 去除所述第三导电层和所述第二绝缘层的部分以形成控制栅极，第二栅极绝缘层，第一开口和第二开口; 在所述基板上形成源极区域; 形成间隔物; 以及在所述衬底上形成漏区。

公开(公告)号：US06451654B1

公开(公告)日：2002-09-17

申请号：US10029429

申请日：2001-12-18

Applicant: Chi-Hui Lin ,  Chung-Lin Huang ,  Yung-Meng Huang

Inventor： Chi-Hui Lin ,  Chung-Lin Huang ,  Yung-Meng Huang

IPC: H01L218247

CPC classification number: H01L27/11521 ,  H01L27/115

Abstract: The present invention provides a process for fabricating a self-aligned split gate flash memory. First, a patterned gate oxide layer, a first patterned polysilicon layer, and a first patterned mask layer are successively formed on a semiconductor substrate, and a first insulating spacer is formed on their sidewalls. Then, shallow trench isolation (STI) is formed in the substrate using the first patterned mask layer and the first insulating spacer as a mask. Then, the first patterned mask layer and a part of the first insulating spacer are removed to expose the first patterned polysilicon layer. A floating gate region is defined on the first patterned polysilicon layer, and the surface of the first polysilicon layer in the floating gate region is selectively oxidized to form polysilicon oxide layer. Then, the polysilicon oxide layer is used as a mask to remove the underlying first polysilicon layer in a self-aligned manner to form a floating gate. Finally, an intergate insulating layer and a second patterned polysilicon layer as a control gate are succesively formed on the polysilicon oxide layer. The present invention forms a floating gate in a self-aligned manner, which can decreases critical dimension. When an oxidation process is conducted to form the above polysilicon oxide layer, the nitride liner layer and the insulating spacer formed in the trench protect the sides of floating gate from oxygen invasion. This prevents the line width of floating gate from size reduction. Current leakage is also be avoided.

Abstract translation: 本发明提供一种用于制造自对准分离栅闪存的方法。 首先，在半导体衬底上依次形成图案化栅极氧化物层，第一图案化多晶硅层和第一图案化掩模层，并且在其侧壁上形成第一绝缘间隔物。 然后，使用第一图案化掩模层和第一绝缘间隔物作为掩模在衬底中形成浅沟槽隔离（STI）。 然后，去除第一图案化掩模层和第一绝缘间隔物的一部分以露出第一图案化多晶硅层。 在第一图案化多晶硅层上限定浮栅区域，并且浮栅区域中的第一多晶硅层的表面被选择性地氧化以形成多晶硅氧化物层。 然后，将多晶硅氧化物层用作掩模，以自对准的方式去除下面的第一多晶硅层以形成浮动栅极。 最后，在多晶硅氧化物层上连续地形成作为控制栅极的栅极绝缘层和第二图案化多晶硅层。 本发明以自对准的方式形成浮动栅极，这可以降低临界尺寸。 当进行氧化处理以形成上述多晶硅氧化物层时，形成在沟槽中的氮化物衬垫层和绝缘衬垫保护浮动栅极的侧面免受氧气侵入。 这样可以防止浮动栅极的线宽缩小。 电流泄漏也被避免。

公开(公告)号：US5989952A

公开(公告)日：1999-11-23

申请号：US934617

申请日：1997-09-22

Applicant: Tean-Sen Jen ,  Shiou-Yu Wang ,  Jia-Shyong Cheng ,  Chi-Hui Lin

Inventor： Tean-Sen Jen ,  Shiou-Yu Wang ,  Jia-Shyong Cheng ,  Chi-Hui Lin

IPC: C12Q1/48 ,  H01L21/02 ,  H01L21/8242 ,  H01L12/8242

CPC classification number: H01L28/92 ,  C12Q1/48 ,  H01L27/10852

Abstract: A method for fabricating a DRAM cell having a crown-type capacitor over a semiconductor substrate is disclosed. The method includes steps of: (a) forming a transistor over the semiconductor substrate; (b) forming an insulating layer over the transistor; (c) selectively etching the insulating layer to form a contact opening; (d) forming a first conducting layer over the insulating layer and filling into the contact opening; (e) forming an etching stop layer and a mask layer over the first conducting layer; (f) pattering the mask layer to form a plurality of openings; (g) forming a dielectric spacer on the sidewall of the mask layer, and removing exposed portions of the etching stop layer; (h) anisotropically etching the mask layer and the first conducting layer by using the dielectric spacer as a mask, to expose, respectively, the etching stop layer and the insulating layer; (i) removing uncovered etching stop layer to expose the first conducting layer; (j) anisotropically etching the first conducting layer to a predetermined depth by using the dielectric spacer as a mask, thereby forming a crown-type storage electrode; (k) removing the dielectric spacer and the etching stop layer; (l) forming a dielectric layer over exposed portions of the storage electrode; and (m) forming a second conducting layer as an opposite electrode over the dielectric layer.

Abstract translation: 公开了一种在半导体衬底上制造具有冠型电容器的DRAM单元的方法。 该方法包括以下步骤：（a）在半导体衬底上形成晶体管; （b）在所述晶体管上形成绝缘层; （c）选择性地蚀刻绝缘层以形成接触开口; （d）在所述绝缘层上形成第一导电层并填充到所述接触开口中; （e）在所述第一导电层上形成蚀刻停止层和掩​​模层; （f）图案掩模层以形成多个开口; （g）在掩模层的侧壁上形成电介质间隔物，去除蚀刻停止层的暴露部分; （h）通过使用电介质间隔物作为掩模，各向异性地蚀刻掩模层和第一导电层，分别暴露蚀刻停止层和绝缘层; （i）去除未覆盖的蚀刻停止层以暴露第一导电层; （j）通过使用电介质间隔物作为掩模，将第一导电层各向异性蚀刻到预定深度，由此形成冠型存储电极; （k）去除电介质间隔物和蚀刻停止层; （l）在所述存储电极的暴露部分上形成介电层; 和（m）在所述电介质层上形成作为相对电极的第二导电层。

公开(公告)号：US20070063260A1

公开(公告)日：2007-03-22

申请号：US11603771

申请日：2006-11-22

Applicant: Ying-Cheng Chuang ,  Chung-Lin Huang ,  Chi-Hui Lin

Inventor： Ying-Cheng Chuang ,  Chung-Lin Huang ,  Chi-Hui Lin

IPC: H01L29/788

CPC classification number: H01L27/11521 ,  H01L21/28273 ,  H01L29/42324 ,  H01L29/7881

Abstract: A floating gate and fabrication method thereof. A semiconductor substrate is provided, on which an oxide layer, a first conducting layer, and a patterned hard mask layer having an opening are sequentially formed. A spacer is formed on the sidewall of the opening. A second conducting layer is formed on the hard mask layer. The second conducting layer is planarized to expose the surface of the patterned hard mask layer. The surface of the second conducting layer is oxidized to form an oxide layer. The patterned hard mask layer and the oxide layer and the first conducting layer underlying the patterned hard mask layer are removed.

Abstract translation: 浮栅及其制造方法。 提供了半导体衬底，其上依次形成有氧化物层，第一导电层和具有开口的图案化硬掩模层。 间隔件形成在开口的侧壁上。 在硬掩模层上形成第二导电层。 将第二导电层平坦化以暴露图案化硬掩模层的表面。 第二导电层的表面被氧化形成氧化物层。 图案化的硬掩模层和氧化物层以及图案化的硬掩模层下面的第一导电层被去除。

公开(公告)号：US07022573B2

公开(公告)日：2006-04-04

申请号：US10884701

申请日：2004-07-02

Applicant: Ching-Nan Hsiao ,  Ying-Cheng Chuang ,  Chi-Hui Lin

Inventor： Ching-Nan Hsiao ,  Ying-Cheng Chuang ,  Chi-Hui Lin

IPC: H01L21/336

CPC classification number: H01L27/11556 ,  H01L27/115 ,  H01L29/42336 ,  H01L29/7881

Abstract: A stacked gate vertical flash memory and a fabrication method thereof. The stacked gate vertical flash memory comprises a semiconductor substrate with a trench, a source conducting layer formed on the bottom of the trench, an insulating layer formed on the source conducting layer, a gate dielectric layer formed on a sidewall of the trench, a conducting spacer covering the gate dielectric layer as a floating gate, an inter-gate dielectric layer covering the conducting spacer, and a control gate conducting layer filled in the trench.

Abstract translation: 堆叠式门垂直闪存及其制造方法。 层叠栅极垂直闪速存储器包括具有沟槽的半导体衬底，形成在沟槽底部的源极导电层，形成在源极导电层上的绝缘层，形成在沟槽侧壁上的栅极电介质层，导电层 覆盖作为浮动栅极的栅极介电层的隔板，覆盖导电间隔物的栅极间介电层和填充在沟槽中的控制栅极导电层。

公开(公告)号：US06998313B2

公开(公告)日：2006-02-14

申请号：US10733626

申请日：2003-12-11

Applicant: Chi-Hui Lin

Inventor： Chi-Hui Lin

IPC: H01L21/336

CPC classification number: H01L27/11556 ,  H01L27/115 ,  H01L29/42336 ,  H01L29/7883

Abstract: A stacked gate flash memory device and method of fabricating the same. A cell of the stacked gate flash memory device is disposed in a cell trench within a substrate to achieve higher integration of memory cells.

公开(公告)号：US06900112B2

公开(公告)日：2005-05-31

申请号：US10426348

申请日：2003-04-30

Applicant: Chi-Hui Lin ,  Chung-Lin Huang

Inventor： Chi-Hui Lin ,  Chung-Lin Huang

IPC: H01L21/762 ,  H01L21/76

CPC classification number: H01L21/76224

Abstract: A process for forming shallow trench isolation region with corner protection layer. A protection layer is formed within the opening that defines the isolation trench as part of the etching mask such that the etching rate of the protection layer is less than the mask layer and the pad insulating layer to the etchant used to remove the mask layer and pad insulating layer. The protection layer is partially removed and left adjacent to the shallow trench isolation region as a corner protection layer after removing the mask layer and pad insulating layer. Thus, the indentation next to the corner of the isolation region is avoided.

Abstract translation: 用于形成具有角保护层的浅沟槽隔离区的工艺。 在开口内形成保护层，其将隔离沟槽定义为蚀刻掩模的一部分，使得保护层的蚀刻速率小于用于去除掩模层和焊盘的掩模层和蚀刻剂的焊盘绝缘层 绝缘层。 在去除掩模层和焊盘绝缘层之后，保护层被部分地去除并且与作为转角保护层的浅沟槽隔离区相邻。 因此，避免了隔离区域的拐角附近的压痕。

公开(公告)号：US20050101090A1

公开(公告)日：2005-05-12

申请号：US11014483

申请日：2004-12-15

Applicant: Ying-Cheng Chuang ,  Chung-Lin Huang ,  Chi-Hui Lin

Inventor： Ying-Cheng Chuang ,  Chung-Lin Huang ,  Chi-Hui Lin

IPC: H01L21/28 ,  H01L29/423 ,  H01L21/336

CPC classification number: H01L29/42324 ,  H01L29/40114

Abstract: A floating gate with multiple tips and a fabrication method thereof. A semiconductor substrate is provided, on which a patterned hard mask layer is formed, wherein the patterned hard mask layer has an opening. A gate dielectric layer and a first conducting layer with a first predetermined thickness are formed on the bottom of the opening. A spacer is formed on the sidewall of the opening. A conducting spacer is formed on the sidewall of the spacer. The first conducting layer is etched to a second predetermined thickness. A multi-tip floating gate is provided by the first conducting layer and the conducting spacer. A protecting layer is formed in the opening. The patterned hard mask layer, the gate dielectric layer, a portion of the protecting layer, and a portion of the first spacer are etched to expose the surface of the first conducting layer.

Abstract translation: 具有多个尖端的浮动栅极及其制造方法。 提供半导体衬底，在其上形成图案化的硬掩模层，其中图案化的硬掩模层具有开口。 在开口的底部形成具有第一预定厚度的栅介质层和第一导电层。 间隔件形成在开口的侧壁上。 导电间隔件形成在间隔件的侧壁上。 第一导电层被蚀刻到第二预定厚度。 由第一导电层和导电间隔物提供多尖端浮栅。 在开口中形成保护层。 蚀刻图案化的硬掩模层，栅介质层，保护层的一部分和第一间隔物的一部分，以露出第一导电层的表面。