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31 条记录 (耗时 0.025 秒)

    High-performance FET device layout
    21.
    发明授权
    High-performance FET device layout 失效
    高性能FET器件布局

    公开(公告)号：US07791160B2

    公开(公告)日：2010-09-07

    申请号：US11923919

    申请日：2007-10-25

    申请人： Jonghae Kim ,  Sungjae Lee ,  Jean-Olivier Plouchart ,  Scott Keith Springer

    发明人： Jonghae Kim ,  Sungjae Lee ,  Jean-Olivier Plouchart ,  Scott Keith Springer

    IPC分类号： H01L29/786

    CPC分类号： H01L27/0207 ,  H01L21/84 ,  H01L29/4238

    摘要： A fast FET, a method and system for designing the fast FET and a design structure of the fast FET. The method includes: selecting a reference design for a field effect transistor, the field effect transistor including a source, a drain, a channel between the source and drain, a gate electrode over the channel, at least one source contact to the source and at least one contact to the drain, the at least one source contact spaced a first distance from the gate electrode and the at least one drain contact spaced a second distance from the gate electrode; and adjusting the first distance and the second distance to maximize a performance parameter of the field effect transistor to create a fast design for the field effect transistor.

    摘要翻译： 一种用于设计快速FET的快速FET，方法和系统以及快速FET的设计结构。 该方法包括：选择场效应晶体管的参考设计，场效应晶体管包括源极，漏极，源极和漏极之间的沟道，沟道上的栅电极，至少一个源极和源极 所述至少一个源极接触件与所述栅电极隔开第一距离，所述至少一个漏极接触件与所述栅电极间隔开第二距离; 并且调整第一距离和第二距离以最大化场效应晶体管的性能参数以产生用于场效应晶体管的快速设计。

    Electrical contact structure having multiple metal interconnect levels staggering one another
    22.
    发明授权
    Electrical contact structure having multiple metal interconnect levels staggering one another 有权
    具有多个金属互连级别彼此交错的电接触结构

    公开(公告)号：US08178908B2

    公开(公告)日：2012-05-15

    申请号：US12116470

    申请日：2008-05-07

    申请人： David Ross Greenberg ,  Jean-Olivier Plouchart ,  Alberto Valdes-Garcia

    发明人： David Ross Greenberg ,  Jean-Olivier Plouchart ,  Alberto Valdes-Garcia

    IPC分类号： H01L29/41

    CPC分类号： H01L27/0207 ,  H01L23/4824 ,  H01L23/528 ,  H01L27/088 ,  H01L29/41758 ,  H01L29/42376 ,  H01L29/4238 ,  H01L29/78 ,  H01L2924/0002 ,  H01L2924/14 ,  H01L2924/30105 ,  H01L2924/00

    摘要： An electrical contact structure distributes current along a length thereof. The electrical contact structure includes a plurality of n metal rectangles on n levels of metal. The rectangle on one metal level is at least as wide in width and vertically covers in width the rectangle on the metal level immediately below. The rectangle on one metal level is shorter in length than and substantially aligned at a first end with the rectangle on the metal level immediately below. Rectangle first ends are substantially aligned. Features of an exemplary FET transistor of this invention are a source and drain terminal electrical contact structure, a multi-level metal ring connecting gate rectangles on both ends, and a wider-than-minimum gate-to-gate spacing. The invention is useful, for example, in an electromigration-compliant, high performance transistor.

    摘要翻译： 电接触结构沿其长度分布电流。 电接触结构包括在n级金属上的多个n个金属矩形。 一个金属层上的矩形至少具有宽度的宽度，并且垂直地在宽度上覆盖紧接在下面的金属层上的矩形。 一个金属层上的矩形长度短于第一端，并且在紧靠下方的金属层上的矩形基本对齐。 矩形的第一端基本对齐。 本发明的示例性FET晶体管的特征是源极和漏极端子电接触结构，在两端连接栅极矩形的多级金属环和大于最小栅极至栅极间隔。 本发明例如在电迁移兼容的高性能晶体管中是有用的。

    Electromigration-Complaint High Performance FET Layout
    23.
    发明申请
    Electromigration-Complaint High Performance FET Layout 有权
    电迁移投诉高性能FET布局

    公开(公告)号：US20090278207A1

    公开(公告)日：2009-11-12

    申请号：US12116470

    申请日：2008-05-07

    申请人： David Ross Greenberg ,  Jean-Olivier Plouchart ,  Alberto Valdes-Garcia

    发明人： David Ross Greenberg ,  Jean-Olivier Plouchart ,  Alberto Valdes-Garcia

    IPC分类号： H01L29/78 ,  H01B5/00

    CPC分类号： H01L27/0207 ,  H01L23/4824 ,  H01L23/528 ,  H01L27/088 ,  H01L29/41758 ,  H01L29/42376 ,  H01L29/4238 ,  H01L29/78 ,  H01L2924/0002 ,  H01L2924/14 ,  H01L2924/30105 ,  H01L2924/00

    摘要： An electrical contact structure distributes current along a length thereof. The electrical contact structure includes a plurality of n metal rectangles on n levels of metal. The rectangle on one metal level is at least as wide in width and vertically covers in width the rectangle on the metal level immediately below. The rectangle on one metal level is shorter in length than and substantially aligned at a first end with the rectangle on the metal level immediately below. Rectangle first ends are substantially aligned. Features of an exemplary FET transistor of this invention are a source and drain terminal electrical contact structure, a multi-level metal ring connecting gate rectangles on both ends, and a wider-than-minimum gate-to-gate spacing. The invention is useful, for example, in an electromigration-compliant, high performance transistor.

    摘要翻译： 电接触结构沿其长度分布电流。 电接触结构包括在n级金属上的多个n个金属矩形。 一个金属层上的矩形至少具有宽度的宽度，并且垂直地在宽度上覆盖紧接在下面的金属层上的矩形。 一个金属层上的矩形长度短于第一端，并且在紧靠下方的金属层上的矩形基本对齐。 矩形的第一端基本对齐。 本发明的示例性FET晶体管的特征是源极和漏极端子电接触结构，在两端连接栅极矩形的多级金属环和大于最小栅极至栅极间隔。 本发明例如在电迁移兼容的高性能晶体管中是有用的。

    Track and Hold Amplifiers and Digital Calibration for Analog-to-Digital Converters
    25.
    发明申请
    Track and Hold Amplifiers and Digital Calibration for Analog-to-Digital Converters 有权
    跟踪和保持放大器和模数转换器的数字校准

    公开(公告)号：US20120188109A1

    公开(公告)日：2012-07-26

    申请号：US13010285

    申请日：2011-01-20

    申请人： Mihai Adrian TIberiu Sanduleanu ,  Jean-Olivier Plouchart ,  Zeynep Toprak Deniz

    发明人： Mihai Adrian TIberiu Sanduleanu ,  Jean-Olivier Plouchart ,  Zeynep Toprak Deniz

    IPC分类号： H03M1/10 ,  G11C27/02

    CPC分类号： G11C27/02 ,  H03M1/1061 ,  H03M1/365

    摘要： An exemplary differential track and hold amplifier includes a track stage including first and second linearized pairs connected in series at their respective inputs and in parallel at their respective outputs. The differential track and hold amplifier also includes a hold stage selectively coupled to the outputs of the first and second linearized pairs. The hold stage includes a unity gain buffer with feedback having a hold capacitor interconnected across its outputs. The differential track and hold amplifier also includes an output buffer coupled to the outputs of the hold stage. An exemplary analog-to-digital converter includes a differential track-and-hold amplifier, a voltage ladder, and a plurality of slices. Each of the slices in turn includes a differential preamplifier coupled to the track-and-hold amplifier and to a corresponding location on the voltage ladder; a current mode logic latch comparator coupled to the differential preamplifier; a large-swing latch coupled to the current mode logic latch comparator; a complementary metal oxide semiconductor latch having a dummy load; a calibration digital to analog converter connected across outputs of the differential preamplifier to inject calibration currents; and a register coupled to the calibration digital to analog converter and storing calibration values for use thereby. The analog-to-digital converter also includes a multiplexer which multiplexes outputs of the complementary metal oxide semiconductor latches down to a predetermined number of outputs.

    摘要翻译： 示例性的差分跟踪和保持放大器包括轨道平台，该轨道平台包括在其各自的输入处并联并联的第一和第二线性化对，并且在它们各自的输出处并联。 差分跟踪和保持放大器还包括选择性地耦合到第一和第二线性化对的输出的保持级。 保持级包括具有反馈的单位增益缓冲器，其具有在其输出端互连的保持电容器。 差分跟踪和保持放大器还包括耦合到保持级的输出的输出缓冲器。 示例性模数转换器包括差分跟踪保持放大器，电压梯和多个片。 每个切片依次包括耦合到跟踪保持放大器和电压梯上相应位置的差分前置放大器; 耦合到差分前置放大器的电流模式逻辑锁存比较器; 耦合到电流模式逻辑锁存比较器的大摆动锁存器; 具有虚拟负载的互补金属氧化物半导体锁存器; 连接在差分前置放大器的输出端的校准数模转换器，以注入校准电流; 以及耦合到校准数模转换器的寄存器，并存储用于其的校准值。 模数转换器还包括多路复用器，其将互补金属氧化物半导体锁存器的输出多路复用到预定数量的输出。

    Systems and Methods for Providing Power to a Device Under Test
    28.
    发明申请
    Systems and Methods for Providing Power to a Device Under Test 审中-公开
    向被测设备供电的系统和方法

    公开(公告)号：US20100259107A1

    公开(公告)日：2010-10-14

    申请号：US12679204

    申请日：2008-11-14

    申请人： Peter Kinget ,  Jean-Olivier Plouchart

    发明人： Peter Kinget ,  Jean-Olivier Plouchart

    IPC分类号： H02J17/00

    CPC分类号： G01R31/315 ,  G01R31/3025

    摘要： Systems and methods for providing power to a device under test are prcn ided. In some embodiments, systems for providing power to a device under test are provided, the systems comprising a power source for providing an alternating current, a probe having a probe inductor coupled to the power source; and a device under test having a device inductor magnetically coupled to the probe inductor, and having a circuit to be tested that receives power produced in the device inductor, In some embodiments, devices that receive power from a probe having an inductor that is coupled to an alternating current power source are provided, the devices comprising: a device inductor magnetically coupled to the probe inductor; and a circuit to be tested that receives power produced in the device inductor.

    摘要翻译： 准备向被测设备供电的系统和方法。 在一些实施例中，提供了用于向受测设备提供电力的系统，所述系统包括用于提供交流电的电源，具有耦合到所述电源的探针电感器的探针; 以及被测器件，其具有与探头电感器磁耦合的器件电感器，并且具有接收在器件电感器中产生的功率的待测试电路。在一些实施例中，从具有耦合到 提供交流电源，所述装置包括：与所述探针电感器磁耦合的器件电感器; 以及接收在器件电感器中产生的功率的待测电路。

    Track and hold amplifiers and digital calibration for analog-to-digital converters
    30.
    发明授权
    Track and hold amplifiers and digital calibration for analog-to-digital converters 有权
    跟踪和保持放大器和模数转换器的数字校准

    公开(公告)号：US08350738B2

    公开(公告)日：2013-01-08

    申请号：US13010285

    申请日：2011-01-20

    申请人： Mihai Adrian Tiberiu Sanduleanu ,  Jean-Olivier Plouchart ,  Zeynep Toprak Deniz

    发明人： Mihai Adrian Tiberiu Sanduleanu ,  Jean-Olivier Plouchart ,  Zeynep Toprak Deniz

    IPC分类号： H03M1/10

    CPC分类号： G11C27/02 ,  H03M1/1061 ,  H03M1/365

    摘要： An exemplary differential track and hold amplifier includes a track stage including first and second linearized pairs connected in series at their respective inputs and in parallel at their respective outputs. The differential track and hold amplifier also includes a hold stage selectively coupled to the outputs of the first and second linearized pairs. The hold stage includes a unity gain buffer with feedback having a hold capacitor interconnected across its outputs. The differential track and hold amplifier also includes an output buffer coupled to the outputs of the hold stage. An exemplary analog-to-digital converter includes a differential track-and-hold amplifier, a voltage ladder, and a plurality of slices. Each of the slices in turn includes a differential preamplifier coupled to the track-and-hold amplifier and to a corresponding location on the voltage ladder; a current mode logic latch comparator coupled to the differential preamplifier; a large-swing latch coupled to the current mode logic latch comparator; a complementary metal oxide semiconductor latch having a dummy load; a calibration digital to analog converter connected across outputs of the differential preamplifier to inject calibration currents; and a register coupled to the calibration digital to analog converter and storing calibration values for use thereby. The analog-to-digital converter also includes a multiplexer which multiplexes outputs of the complementary metal oxide semiconductor latches down to a predetermined number of outputs.

    摘要翻译： 示例性的差分跟踪和保持放大器包括轨道平台，该轨道平台包括在其各自的输入处并联并联的第一和第二线性化对，并且在它们各自的输出处并联。 差分跟踪和保持放大器还包括选择性地耦合到第一和第二线性化对的输出的保持级。 保持级包括具有反馈的单位增益缓冲器，其具有在其输出端互连的保持电容器。 差分跟踪和保持放大器还包括耦合到保持级的输出的输出缓冲器。 示例性模数转换器包括差分跟踪保持放大器，电压梯和多个片。 每个切片依次包括耦合到跟踪保持放大器和电压梯上相应位置的差分前置放大器; 耦合到差分前置放大器的电流模式逻辑锁存比较器; 耦合到电流模式逻辑锁存比较器的大摆动锁存器; 具有虚拟负载的互补金属氧化物半导体锁存器; 连接在差分前置放大器的输出端的校准数模转换器，以注入校准电流; 以及耦合到校准数模转换器的寄存器，并存储用于其的校准值。 模数转换器还包括多路复用器，其将互补金属氧化物半导体锁存器的输出多路复用到预定数量的输出。