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公开(公告)号：US20120223411A1
公开(公告)日：2012-09-06
申请号：US13469464
申请日：2012-05-11
申请人： Choongyeun Cho , Daeik Kim , Jonghae Kim , Moon J. Kim , Jean-Olivier Plouchart , Robert E. Trzcinski
发明人： Choongyeun Cho , Daeik Kim , Jonghae Kim , Moon J. Kim , Jean-Olivier Plouchart , Robert E. Trzcinski
CPC分类号： H01L28/10 , H01F17/0013 , H01F2017/0073 , H01L23/5227 , H01L27/0203 , H01L2924/0002 , H01L2924/00
摘要： Sub-100 nanometer semiconductor devices and methods and program products for manufacturing devices are provided, in particular inductors comprising a plurality of spaced parallel metal lines disposed on a dielectric surface and each having width, heights, spacing and cross-sectional areas determined as a function of Design Rule Check rules. For one planarization process rule a metal density ratio of 80% metal to 20% dielectric surface is determined and produced. In one example a sum of metal line spacing gaps is less than a sum of metal line interior sidewall heights. In one aspect at least one of line height, width and line spacing dimensions is selected to optimize one or more chip yield, chip performance, chip manufacturability and inductor Q factor parameters.
摘要翻译： 提供了用于制造器件的亚100纳米半导体器件和方法和程序产品，特别是电感器，其包括设置在电介质表面上的多个间隔开的平行金属线，并且每个具有确定为功能的宽度，高度，间隔和横截面面积 的设计规则检查规则。 对于一个平面化工艺规则，确定并生产了80％金属至20％电介质表面的金属密度比。 在一个示例中，金属线间距的总和小于金属线内侧壁高度的总和。 在一个方面，选择线高度，宽度和线间距尺寸中的至少一个以优化一个或多个芯片产量，芯片性能，芯片制造性和电感器Q因子参数。
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公开(公告)号：US08227891B2
公开(公告)日：2012-07-24
申请号：US12362877
申请日：2009-01-30
申请人： Choongyeun Cho , Daeik Kim , Jonghae Kim , Moon J. Kim , Jean-Olivier Plouchart , Robert E. Trzcinski
发明人： Choongyeun Cho , Daeik Kim , Jonghae Kim , Moon J. Kim , Jean-Olivier Plouchart , Robert E. Trzcinski
IPC分类号： H01L21/00
CPC分类号： H01L28/10 , H01F17/0013 , H01F2017/0073 , H01L23/5227 , H01L27/0203 , H01L2924/0002 , H01L2924/00
摘要： Sub-100 nanometer semiconductor devices and methods and program products for manufacturing devices are provided, in particular inductors comprising a plurality of spaced parallel metal lines disposed on a dielectric surface and each having width, heights, spacing and cross-sectional areas determined as a function of Design Rule Check rules. For one planarization process rule a metal density ratio of 80% metal to 20% dielectric surface is determined and produced. In one example a sum of metal line spacing gaps is less than a sum of metal line interior sidewall heights. In one aspect at least one of line height, width and line spacing dimensions is selected to optimize one or more chip yield, chip performance, chip manufacturability and inductor Q factor parameters.
摘要翻译： 提供了用于制造器件的亚100纳米半导体器件和方法和程序产品，特别是电感器，其包括设置在电介质表面上的多个间隔开的平行金属线，并且每个具有确定为功能的宽度，高度，间隔和横截面面积 的设计规则检查规则。 对于一个平面化工艺规则，确定并生产了80％金属至20％电介质表面的金属密度比。 在一个示例中，金属线间距的总和小于金属线内侧壁高度的总和。 在一个方面，选择线高度，宽度和线间距尺寸中的至少一个以优化一个或多个芯片产量，芯片性能，芯片制造性和电感器Q因子参数。
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公开(公告)号：US20070123015A1
公开(公告)日：2007-05-31
申请号：US11164634
申请日：2005-11-30
申请人： Anil Chinthakindi , Douglas Coolbaugh , Ebenezer Eshun , Zhong-Xiang He , Jeffrey Johnson , Jonghae Kim , Jean-Olivier Plouchart , Anthony Stamper
发明人： Anil Chinthakindi , Douglas Coolbaugh , Ebenezer Eshun , Zhong-Xiang He , Jeffrey Johnson , Jonghae Kim , Jean-Olivier Plouchart , Anthony Stamper
CPC分类号： H01L23/5228 , H01L23/5227 , H01L28/87 , H01L2924/0002 , H01L2924/00
摘要： Passive components are formed in the back end by using the same deposition process and materials as in the rest of the back end. Resistors are formed by connecting in series individual structures on the nth, (n+1)th, etc levels of the back end. Capacitors are formed by constructing a set of vertical capacitor plates from a plurality of levels in the back end, the plates being formed by connecting electrodes on two or more levels of the back end by vertical connection members.
摘要翻译： 通过使用与后端的其余部分相同的沉积工艺和材料在后端形成被动部件。 电阻器通过连接在后端的第n（n + 1）等级上的串联单独结构而形成。 电容器通过从后端的多个层构造一组垂直电容器板而形成，该板通过垂直连接构件在后端的两层或更多层上连接电极而形成。
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5.发明授权Electrical contact structure having multiple metal interconnect levels staggering one another 有权具有多个金属互连级别彼此交错的电接触结构公开(公告)号：US08178908B2
公开(公告)日：2012-05-15
申请号：US12116470
申请日：2008-05-07
IPC分类号： H01L29/41
CPC分类号： H01L27/0207 , H01L23/4824 , H01L23/528 , H01L27/088 , H01L29/41758 , H01L29/42376 , H01L29/4238 , H01L29/78 , H01L2924/0002 , H01L2924/14 , H01L2924/30105 , H01L2924/00
摘要： An electrical contact structure distributes current along a length thereof. The electrical contact structure includes a plurality of n metal rectangles on n levels of metal. The rectangle on one metal level is at least as wide in width and vertically covers in width the rectangle on the metal level immediately below. The rectangle on one metal level is shorter in length than and substantially aligned at a first end with the rectangle on the metal level immediately below. Rectangle first ends are substantially aligned. Features of an exemplary FET transistor of this invention are a source and drain terminal electrical contact structure, a multi-level metal ring connecting gate rectangles on both ends, and a wider-than-minimum gate-to-gate spacing. The invention is useful, for example, in an electromigration-compliant, high performance transistor.
摘要翻译： 电接触结构沿其长度分布电流。 电接触结构包括在n级金属上的多个n个金属矩形。 一个金属层上的矩形至少具有宽度的宽度，并且垂直地在宽度上覆盖紧接在下面的金属层上的矩形。 一个金属层上的矩形长度短于第一端，并且在紧靠下方的金属层上的矩形基本对齐。 矩形的第一端基本对齐。 本发明的示例性FET晶体管的特征是源极和漏极端子电接触结构，在两端连接栅极矩形的多级金属环和大于最小栅极至栅极间隔。 本发明例如在电迁移兼容的高性能晶体管中是有用的。
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公开(公告)号：US20090278207A1
公开(公告)日：2009-11-12
申请号：US12116470
申请日：2008-05-07
CPC分类号： H01L27/0207 , H01L23/4824 , H01L23/528 , H01L27/088 , H01L29/41758 , H01L29/42376 , H01L29/4238 , H01L29/78 , H01L2924/0002 , H01L2924/14 , H01L2924/30105 , H01L2924/00
摘要： An electrical contact structure distributes current along a length thereof. The electrical contact structure includes a plurality of n metal rectangles on n levels of metal. The rectangle on one metal level is at least as wide in width and vertically covers in width the rectangle on the metal level immediately below. The rectangle on one metal level is shorter in length than and substantially aligned at a first end with the rectangle on the metal level immediately below. Rectangle first ends are substantially aligned. Features of an exemplary FET transistor of this invention are a source and drain terminal electrical contact structure, a multi-level metal ring connecting gate rectangles on both ends, and a wider-than-minimum gate-to-gate spacing. The invention is useful, for example, in an electromigration-compliant, high performance transistor.
摘要翻译： 电接触结构沿其长度分布电流。 电接触结构包括在n级金属上的多个n个金属矩形。 一个金属层上的矩形至少具有宽度的宽度，并且垂直地在宽度上覆盖紧接在下面的金属层上的矩形。 一个金属层上的矩形长度短于第一端，并且在紧靠下方的金属层上的矩形基本对齐。 矩形的第一端基本对齐。 本发明的示例性FET晶体管的特征是源极和漏极端子电接触结构，在两端连接栅极矩形的多级金属环和大于最小栅极至栅极间隔。 本发明例如在电迁移兼容的高性能晶体管中是有用的。
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公开(公告)号：US07518850B2
公开(公告)日：2009-04-14
申请号：US11436248
申请日：2006-05-18
IPC分类号： H01G4/38 , H01G4/00 , H01L27/108 , H01L29/94 , H01L21/20
CPC分类号： H01L27/0811 , H01L23/5223 , H01L27/0688 , H01L27/0805 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： A capacitance circuit assembly mounted on a semiconductor chip, and methods for forming the same, are provided. A plurality of divergent capacitors is provided in a parallel circuit connection between first and second ports, the plurality providing at least one Metal Oxide Silicon Capacitor and at least one Vertical Native Capacitor or Metal-Insulator-Metal Capacitor. An assembly has a vertical orientation, a Metal Oxide Silicon capacitor located at the bottom and defining a footprint, with a middle Vertical Native Capacitor having a plurality of horizontal metal layers, including a plurality of parallel positive plates alternating with a plurality of parallel negative plates. In another aspect, vertically asymmetric orientations provide a reduced total parasitic capacitance.
摘要翻译： 设置安装在半导体芯片上的电容电路组件及其形成方法。 多个发散电容器设置在第一和第二端口之间的并联电路连接中，多个提供至少一个金属氧化物硅电容器和至少一个垂直本机电容器或金属绝缘体金属电容器。 组件具有垂直取向，金属氧化物硅电容器位于底部并限定占地面积，中间垂直本机电容器具有多个水平金属层，包括多个平行的正极板，与多个平行的负极板交替 。 在另一方面，垂直不对称取向提供减小的总寄生电容。
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公开(公告)号：US07504705B2
公开(公告)日：2009-03-17
申请号：US11536896
申请日：2006-09-29
申请人： Choongyeun Cho , Daeik Kim , Jonghae Kim , Moon J. Kim , Jean-Olivier Plouchart , Robert E. Trzcinski
发明人： Choongyeun Cho , Daeik Kim , Jonghae Kim , Moon J. Kim , Jean-Olivier Plouchart , Robert E. Trzcinski
IPC分类号： G06F17/50
CPC分类号： H01L28/10 , H01F17/0013 , H01F2017/0073 , H01L23/5227 , H01L27/0203 , H01L2924/0002 , H01L2924/00
摘要： Sub-100 nanometer semiconductor devices and methods and program products for manufacturing devices are provided, in particular inductors comprising a plurality of spaced parallel metal lines disposed on a dielectric surface and each having width, heights, spacing and cross-sectional areas determined as a function of Design Rule Check rules. For one planarization process rule a metal density ratio of 80% metal to 20% dielectric surface is determined and produced. In one example a sum of metal line spacing gaps is less than a sum of metal line interior sidewall heights. In one aspect at least one of line height, width and line spacing dimensions is selected to optimize one or more chip yield, chip performance, chip manufacturability and inductor Q factor parameters.
摘要翻译： 提供了用于制造器件的亚100纳米半导体器件和方法和程序产品，特别是电感器，其包括设置在电介质表面上的多个间隔开的平行金属线，并且每个具有确定为功能的宽度，高度，间隔和横截面面积 的设计规则检查规则。 对于一个平面化工艺规则，确定并生产了80％金属至20％电介质表面的金属密度比。 在一个示例中，金属线间距的总和小于金属线内侧壁高度的总和。 在一个方面，选择线高度，宽度和线间距尺寸中的至少一个以优化一个或多个芯片产量，芯片性能，芯片制造性和电感器Q因子参数。
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公开(公告)号：US20070268653A1
公开(公告)日：2007-11-22
申请号：US11436248
申请日：2006-05-18
IPC分类号： H01G4/38
CPC分类号： H01L27/0811 , H01L23/5223 , H01L27/0688 , H01L27/0805 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： A capacitance circuit assembly mounted on a semiconductor chip, and method for forming the same, comprising a plurality of divergent capacitors in a parallel circuit connection between first and second ports, the plurality comprising at least one Metal Oxide Silicon Capacitor and at least one capacitor selected from the group comprising a Vertical Native Capacitor and a Metal-Insulator-Metal Capacitor. In one aspect, the assembly has vertical orientation, the Metal Oxide Silicon capacitor located at the bottom and defining the footprint, middle Vertical Native Capacitor comprising a plurality of horizontal metal layers comprising a plurality of parallel positive plates alternating with a plurality of parallel negative plates. In another aspect, a vertically asymmetric orientation provides a reduced total parasitic capacitance.
摘要翻译： 安装在半导体芯片上的电容电路组件及其形成方法包括在第一和第二端口之间的并联电路连接中的多个发散电容器，多个包括至少一个金属氧化物硅电容器和至少一个选择的电容器 来自包括垂直本机电容器和金属 - 绝缘体 - 金属电容器的组。 在一个方面，组件具有垂直取向，金属氧化物硅电容器位于底部并限定占用面积，中间垂直本机电容器包括多个水平金属层，其包括多个平行的正极板，与多个平行的负极板 。 在另一方面，垂直非对称取向提供减小的总寄生电容。
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公开(公告)号：US08648454B2
公开(公告)日：2014-02-11
申请号：US13396030
申请日：2012-02-14
IPC分类号： H01L23/48
CPC分类号： G06K19/07775 , H01L23/5225 , H01L23/5227 , H01L23/66 , H01L24/13 , H01L24/16 , H01L24/32 , H01L24/48 , H01L24/73 , H01L27/14618 , H01L2223/6627 , H01L2223/6677 , H01L2224/0401 , H01L2224/04042 , H01L2224/05009 , H01L2224/13025 , H01L2224/16225 , H01L2224/32225 , H01L2224/451 , H01L2224/48091 , H01L2224/48227 , H01L2224/73253 , H01L2224/73265 , H01L2924/00014 , H01L2924/1421 , H01L2924/15192 , H01L2924/15311 , H01L2924/19104 , H01L2924/19107 , H01Q1/2283 , H01Q9/0407 , H01L2924/00 , H01L2224/45099 , H01L2224/05599
摘要： Wafer-scale packaging structures and methods are provided for integrally packaging antenna structures with semiconductor RFIC (radio frequency integrated circuit) chips to form compact integrated radio/wireless communications systems for millimeter wave (mmWave) and Terahertz (THz) applications. For example, a chip package includes an RFIC chip, an antenna structure and an interface layer. The RFIC chip includes a semiconductor substrate having an active surface and an inactive surface, and a BEOL (back end of line) structure formed on the active surface of the semiconductor substrate. The antenna structure includes an antenna substrate and a planar antenna radiator formed on a surface of the antenna substrate, wherein the antenna substrate is formed of a low loss semiconductor material. The interface layer connects the antenna structure to the BEOL structure of the RFIC chip.
摘要翻译： 提供了用于将天线结构与半导体RFIC（射频集成电路）芯片整体封装在一起的晶片级封装结构和方法，以形成用于毫米波（mmWave）和太赫兹（THz）应用的紧凑的集成无线电/无线通信系统。 例如，芯片封装包括RFIC芯片，天线结构和接口层。 RFIC芯片包括具有活性表面和非活性表面的半导体衬底，以及形成在半导体衬底的有源表面上的BEOL（后端）结构。 天线结构包括天线基板和形成在天线基板的表面上的平面天线辐射器，其中天线基板由低损耗半导体材料形成。 接口层将天线结构连接到RFIC芯片的BEOL结构。
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