公开(公告)号：US06762974B1

公开(公告)日：2004-07-13

申请号：US10389807

申请日：2003-03-18

申请人： Brian Johnson ,  Brent Keeth ,  Feng Lin

发明人： Brian Johnson ,  Brent Keeth ,  Feng Lin

IPC分类号： G11C800

CPC分类号： G11C7/222 ,  G11C7/1072 ,  G11C11/4076

摘要： A method and apparatus for managing the variable timing of internal clock signals derived from an external clock signal in order to compensate for uncertainty and variations in the amount of read clock back timing relative to data flow to achieve a specified read latency. A reset signal is generated at DRAM initialization and starts an first counter, which counts external clock cycles, and is also passed through the slave delay line of the delay lock loop to start a second counter. The counters run continuously once started and the difference in count values represent the internal delay as an external clock signal passes through the delay lock loop to produce an internal read clock signal. An internal read latency value is used to offset either counter to account for the internal read latency of the DRAM circuit. Once the non-offset counter is equivalent to the offset counter, read data is placed on an output line with a specified read latency and synchronized with the external read clock.

摘要翻译： 一种用于管理从外部时钟信号导出的内部时钟信号的可变定时的方法和装置，以便补偿相对于数据流的读取时钟反馈时序的不确定性和变化，以实现指定的读取等待时间。 在DRAM初始化时产生复位信号，并启动计数外部时钟周期的第一计数器，并且还通过延迟锁定循环的从延迟线来启动第二个计数器。 一旦启动，计数器连续运行，当外部时钟信号通过延迟锁定环路以产生内部读取时钟信号时，计数值的差异代表内部延迟。 内部读延迟值用于抵消DRAM电路的内部读延迟。 一旦非偏移计数器等效于偏移计数器，读取数据将放置在具有指定读延迟并与外部读时钟同步的输出线上。

公开(公告)号：US06693836B2

公开(公告)日：2004-02-17

申请号：US10278528

申请日：2002-10-22

申请人： Brent Keeth ,  Brian Johnson ,  Troy A. Manning

发明人： Brent Keeth ,  Brian Johnson ,  Troy A. Manning

IPC分类号： G11C700

CPC分类号： G11C7/1072 ,  G11C7/1006 ,  G11C7/1018 ,  G11C7/1027 ,  G11C7/1045 ,  G11C7/1048 ,  G11C7/1051 ,  G11C7/106 ,  G11C7/1066 ,  G11C7/1069 ,  G11C7/1078 ,  G11C11/4093 ,  G11C11/4096 ,  G11C2207/107

摘要： A memory device is operable in either a high mode or a low speed mode. In either mode, 32 bits of data from each of two memory arrays are prefetched into respective sets of 32 flip-flops. In the high-speed mode, the prefetched data bits are transferred in parallel to 4 parallel-to-serial converters, which transform the parallel data bits to a burst of 8 serial data bits and apply the burst to a respective one of 4 data bus terminals. In the low speed mode, two sets of prefetched data bits are transferred in parallel to 8 parallel-to-serial converters, which transform the parallel data bits to a burst of 8 serial data bits and apply the burst to a respective one of 8 data bus terminals.

摘要翻译： 存储器件可以在高模式或低速模式下操作。 在任一模式中，来自两个存储器阵列中的每一个的32位数据被预取到相应的32个触发器组中。 在高速模式下，预取数据位并行传输到4个并行到串行转换器，它们将并行数据位转换为8个串行数据位的脉冲串，并将该脉冲串应用于4个数据总线 终端。 在低速模式下，两组预取数据位并行传送到8个并行到串行转换器，它们将并行数据位转换为8个串行数据位的脉冲串，并将该脉冲串应用于8个数据中的相应一个 巴士总站。

公开(公告)号：US06690609B2

公开(公告)日：2004-02-10

申请号：US10278529

申请日：2002-10-22

申请人： Brent Keeth ,  Brian Johnson ,  Troy A. Manning

发明人： Brent Keeth ,  Brian Johnson ,  Troy A. Manning

IPC分类号： G11C700

CPC分类号： G11C7/1072 ,  G11C7/1006 ,  G11C7/1018 ,  G11C7/1027 ,  G11C7/1045 ,  G11C7/1048 ,  G11C7/1051 ,  G11C7/106 ,  G11C7/1066 ,  G11C7/1069 ,  G11C7/1078 ,  G11C11/4093 ,  G11C11/4096 ,  G11C2207/107

摘要： A memory device is operable in either a high mode or a low speed mode. In either mode 32 bits of data from each of two memory arrays are prefetched into respective sets of 32 flip-flops. In the high-speed mode, the prefetched data bits are transferred in parallel to 4 parallel-to-serial converters, which transform the parallel data bits to a burst of 8 serial data bits and apply the burst to a respective one of 4 data bus terminals. In the low speed mode, two sets of prefetched data bits are transferred in parallel to 8 parallel-to-serial converters, which transform the parallel data bits to a burst of 8 serial data bits and apply the burst to a respective one of 8 data bus terminals.

摘要翻译： 存储器件可以在高模式或低速模式下操作。 在任一模式中，来自两个存储器阵列中的每一个的32位数据被预取到相应的32个触发器组中。 在高速模式下，预取数据位并行传输到4个并行到串行转换器，它们将并行数据位转换为8个串行数据位的脉冲串，并将该脉冲串应用于4个数据总线 终端。 在低速模式下，两组预取数据位并行传送到8个并行到串行转换器，它们将并行数据位转换为8个串行数据位的脉冲串，并将该脉冲串应用于8个数据中的相应一个 巴士总站。

公开(公告)号：US06687185B1

公开(公告)日：2004-02-03

申请号：US10230221

申请日：2002-08-29

申请人： Brent Keeth ,  Brian Johnson ,  Feng Lin

发明人： Brent Keeth ,  Brian Johnson ,  Feng Lin

IPC分类号： G11C800

CPC分类号： G11C7/106 ,  G11C7/1051 ,  G11C7/1066 ,  G11C11/4076 ,  G11C2207/2281

摘要： An apparatus and method for coordinating the variable timing of internal clock signals derived from an external clock signal to ensure that read data and a read clock used to latch the read data arrive at the data latch in synchronism and with a specified read latency. A read clock is produced from the external clock signal in a delay lock loop circuit and a start signal, produced in response to a read command, is passed through a delay circuit slaved with the delay lock loop so that the read clock signal and a delayed start signal are subject to the same internal timing variations. The delayed start signal is used to thereby control the output of read data by the read clock signal.

摘要翻译： 一种用于协调从外部时钟信号导出的内部时钟信号的可变定时的装置和方法，以确保读取数据和用于锁存读取数据的读取时钟同步并以指定的读取延迟到达数据锁存器。 在延迟锁定环路电路中，从外部时钟信号产生读时钟，并且响应于读命令产生的起始信号通过与延迟锁定环相对应的延迟电路，使得读时钟信号和延迟 启动信号受到相同的内部时序变化。 延迟启动信号用于通过读时钟信号控制读数据的输出。

公开(公告)号：US06674378B2

公开(公告)日：2004-01-06

申请号：US10365399

申请日：2003-02-13

申请人： Brian Johnson ,  Brent Keeth

发明人： Brian Johnson ,  Brent Keeth

IPC分类号： H03M110

CPC分类号： G11C11/4076 ,  G11C7/1072 ,  G11C2207/2254

摘要： The present invention provides a unique way of using a 2N bit synchronization pattern to obtain a faster and more reliable calibration of multiple data paths in a memory system. If the 2N bit synchronization pattern is generated with a known clock phase relationship, then the data-to-clock phase alignment can be determined using simple decode logic to predict the next m-bits from a just-detected m-bits. If the succeeding m-bit pattern does not match the predicted pattern, then the current data-to-clock alignment fails for a particular delay value adjustment in the data path undergoing alignment, and the delay in that data path is adjusted to a new value. The invention also ensures that data alignment will occur to a desired edge of the clock signal, e.g., a positive going edge, by forcing a failure of all predicted m-bit patterns which are associated with an undesired edge, e.g., a negative going edge, of the clock signal.

摘要翻译： 本发明提供使用2＆lt; N＆gt;位同步模式以获得存储器系统中的多个数据路径的更快更可靠的校准的独特方式。 如果以已知的时钟相位关系产生2 位同步模式，则可以使用简单的解码逻辑来确定数据到时钟相位对准，以便从刚刚检测到的m位来预测下一个m位。 如果后续的m位模式与预测模式不匹配，则对于经历对准的数据路径中的特定延迟值调整，当前数据对时钟对准失败，并且该数据路径中的延迟被调整到新值 。 本发明还确保通过强制与不期望的边缘相关联的所有预测的m位模式的故障（例如，正向沿），时钟信号的期望边缘（例如，正向边缘）将发生数据对准 的时钟信号。

公开(公告)号：US06434081B1

公开(公告)日：2002-08-13

申请号：US09570481

申请日：2000-05-12

申请人： Brian Johnson ,  Brent Keeth

发明人： Brian Johnson ,  Brent Keeth

IPC分类号： G11C800

CPC分类号： G11C7/1066 ,  G11C7/1018 ,  G11C7/1039 ,  G11C7/1072 ,  G11C7/20 ,  G11C7/22 ,  G11C11/4072

摘要： Disclosed is an improved start-up/reset calibration apparatus and method for use in a memory device One of a plurality of data paths is bit wise calibrated relative to a clock signal and thereafter others of the plurality of data paths are bit wise aligned to a previously calibrated data path to produce serial and parallel bit alignment on all data paths.

摘要翻译： 公开了一种用于存储器装置的改进的启动/复位校准装置和方法多个数据路径中的一个相对于时钟信号进行比特校准，此后多个数据路径中的其他数据路径与 先前校准的数据路径，以在所有数据路径上产生串行和并行位对齐。

公开(公告)号：US07746959B2

公开(公告)日：2010-06-29

申请号：US11433322

申请日：2006-05-11

申请人： Brent Keeth ,  Joo S. Choi ,  George E. Pax ,  Ronnie M. Harrison ,  David Ovard ,  Dragos Dimitriu ,  Troy A. Manning ,  Roy E. Greeff ,  Greg King ,  Brian Johnson

发明人： Brent Keeth ,  Joo S. Choi ,  George E. Pax ,  Ronnie M. Harrison ,  David Ovard ,  Dragos Dimitriu ,  Troy A. Manning ,  Roy E. Greeff ,  Greg King ,  Brian Johnson

IPC分类号： H04L25/06

CPC分类号： H04L25/062

摘要： A method and system for generating a reference voltage for memory device signal receivers operates in either a calibration mode or a normal operating mode. In the calibration mode, the magnitude of the reference voltage is incrementally varied, and a digital signal pattern is coupled to the receiver at each reference voltage. An output of the receiver is analyzed to determine if the receiver can accurately pass the signal pattern at each reference voltage level. A range of reference voltages that allow the receiver to accurately pass the signal pattern is recorded, and a final reference voltage is calculated at the approximate midpoint of the range. This final reference voltage is applied to the receiver during normal operation.

摘要翻译： 用于产生用于存储器件信号接收器的参考电压的方法和系统以校准模式或正常操作模式工作。 在校准模式下，参考电压的幅度逐渐变化，并且数字信号图案在每个参考电压下耦合到接收器。 分析接收机的输出以确定接收机是否可以在每个参考电压电平下准确地传递信号模式。 记录允许接收器精确地通过信号图案的参考电压范围，并且在该范围的大致中点处计算最终参考电压。 在正常操作期间将该最终参考电压施加到接收器。

公开(公告)号：US20070058469A1

公开(公告)日：2007-03-15

申请号：US11595515

申请日：2006-11-08

申请人： Brent Keeth ,  Brian Johnson ,  Troy Manning

发明人： Brent Keeth ,  Brian Johnson ,  Troy Manning

IPC分类号： G11C7/00

CPC分类号： G11C7/1072 ,  G11C7/1006 ,  G11C7/1018 ,  G11C7/1027 ,  G11C7/1045 ,  G11C7/1048 ,  G11C7/1051 ,  G11C7/106 ,  G11C7/1066 ,  G11C7/1069 ,  G11C7/1078 ,  G11C11/4093 ,  G11C11/4096 ,  G11C2207/107

摘要： A memory device is operable in either a high mode or a low speed mode. In either mode 32 bits of data from each of two memory arrays are prefetched into respective sets of 32 flip-flops. In the high-speed mode, the prefetched data bits are transferred in parallel to 4 parallel-to-serial converters, which transform the parallel data bits to a burst of 8 serial data bits and apply the burst to a respective one of 4 data bus terminals. In the low speed mode, two sets of prefetched data bits are transferred in parallel to 8 parallel-to-serial converters, which transform the parallel data bits to a burst of 8 serial data bits and apply the burst to a respective one of 8 data bus terminals.

摘要翻译： 存储器件可以在高模式或低速模式下操作。 在任一模式中，来自两个存储器阵列中的每一个的32位数据被预取到相应的32个触发器组中。 在高速模式下，预取数据位并行传输到4个并行到串行转换器，它们将并行数据位转换为8个串行数据位的脉冲串，并将该脉冲串应用于4个数据总线 终端。 在低速模式下，两组预取数据位并行传送到8个并行到串行转换器，它们将并行数据位转换为8个串行数据位的脉冲串，并将该脉冲串应用于8个数据中的相应一个 巴士总站。

公开(公告)号：US07187617B2

公开(公告)日：2007-03-06

申请号：US11351836

申请日：2006-02-10

申请人： Feng Lin ,  Brent Keeth ,  Brian Johnson ,  Seong-hoon Lee

发明人： Feng Lin ,  Brent Keeth ,  Brian Johnson ,  Seong-hoon Lee

IPC分类号： G11C8/00

CPC分类号： G11C7/109 ,  G11C7/1006 ,  G11C7/1078 ,  G11C7/1087 ,  G11C7/22 ,  G11C7/222

摘要： A memory system couples command, address or write data signals from a memory controller to a memory device and read data signals from the memory device to the memory controller. A respective strobe generator circuit in each of the memory controller and the memory device each generates an in-phase strobe signal and a quadrature strobe signal. Command, address or write data signals stored in respective output latches in the memory controller are clocked by the in-phase signals from the internal strobe generator circuit. These command, address or write data signals are latched into input latches in the memory device by the quadrature strobe signal coupled from the memory controller to the memory device. In substantially the same manner, read data signals are coupled from the memory device to the memory controller using the in-phase and quadrature strobe signals generated by the internal strobe generator circuit.

公开(公告)号：US20060203938A1

公开(公告)日：2006-09-14

申请号：US11433322

申请日：2006-05-11

申请人： Brent Keeth ,  Joo Choi ,  George Pax ,  Ronnie Harrison ,  David Ovard ,  Dragos Dimitriu ,  Troy Manning ,  Roy Greeff ,  Greg King ,  Brian Johnson

发明人： Brent Keeth ,  Joo Choi ,  George Pax ,  Ronnie Harrison ,  David Ovard ,  Dragos Dimitriu ,  Troy Manning ,  Roy Greeff ,  Greg King ,  Brian Johnson

IPC分类号： H04L25/06

CPC分类号： H04L25/062

摘要： A method and system for generating a reference voltage for memory device signal receivers operates in either a calibration mode or a normal operating mode. In the calibration mode, the magnitude of the reference voltage is incrementally varied, and a digital signal pattern is coupled to the receiver at each reference voltage. An output of the receiver is analyzed to determine if the receiver can accurately pass the signal pattern at each reference voltage level. A range of reference voltages that allow the receiver to accurately pass the signal pattern is recorded, and a final reference voltage is calculated at the approximate midpoint of the range. This final reference voltage is applied to the receiver during normal operation.