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公开(公告)号：US20130141992A1
公开(公告)日：2013-06-06
申请号：US13312867
申请日：2011-12-06
IPC分类号： G11C7/00
CPC分类号： G11C14/0054 , G11C7/18 , G11C11/419
摘要： A memory includes an array of memory cells that form rows and columns. The rows of the array include memory cell pairs. The memory cells may include two cross-coupled inverters and two pass-devices that couple to alternate sides of the cross-coupled inverters. The two memory cells of a memory cell pair share a common intra-pair bitline. Adjacent memory cell pairs share a common inter-pair bitline. To perform a data read operation on a particular memory cell in a memory cell pair in the rows and columns of the array, wordline drive circuitry transmits wordline activate signals to select both the row for the data read operation and a particular one of the pair of memory cells for the data read operation.
摘要翻译： 存储器包括形成行和列的存储器单元阵列。 阵列的行包括存储单元对。 存储器单元可以包括耦合到交叉耦合的反相器的交替侧的两个交叉耦合的反相器和两个通过装置。 存储器单元对的两个存储单元共享共同的对内位线。 相邻的存储单元对共享一个共同的对对位线。 为了对阵列的行和列中的存储单元对中的特定存储器单元执行数据读取操作，字线驱动电路传输字线激活信号以选择用于数据读取操作的行和该对中的特定一个 用于数据读取操作的存储单元。
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公开(公告)号：US07936198B2
公开(公告)日：2011-05-03
申请号：US12345758
申请日：2008-12-30
IPC分类号： H03K3/00
CPC分类号： G06F1/04
摘要： A programmable clock control circuit includes a base block, a chop block, and a pulse width variation block coupled between the chop block and the base block that receives the chop block output and provides a pulse width variation output to the base block. The pulse width variation block is programmable to vary the chop block output to provide at least three different output pulse widths. The circuit also includes a clock delay block coupled an output of the base block to delay the output pulse and having a clock signal output.
摘要翻译： 可编程时钟控制电路包括：接收斩波块输出的斩波块与基地块之间的基本块，斩波块和脉冲宽度变化块，并向基地块提供脉冲宽度变化输出。 脉冲宽度变化块可编程以改变斩波块输出以提供至少三个不同的输出脉冲宽度。 该电路还包括一个与基本块的输出相连的时钟延迟块，以延迟输出脉冲并具有时钟信号输出。
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公开(公告)号：US20100164586A1
公开(公告)日：2010-07-01
申请号：US12345758
申请日：2008-12-30
IPC分类号： H03H11/26
CPC分类号： G06F1/04
摘要： A programmable clock control circuit includes a base block, a chop block, and a pulse width variation block coupled between the chop block and the base block that receives the chop block output and provides a pulse width variation output to the base block. The pulse width variation block is programmable to vary the chop block output to provide at least three different output pulse widths. The circuit also includes a clock delay block coupled an output of the base block to delay the output pulse and having a clock signal output.
摘要翻译： 可编程时钟控制电路包括：接收斩波块输出的斩波块与基地块之间的基本块，斩波块和脉冲宽度变化块，并向基地块提供脉冲宽度变化输出。 脉冲宽度变化块可编程以改变斩波块输出以提供至少三个不同的输出脉冲宽度。 该电路还包括一个与基本块的输出相连的时钟延迟块，以延迟输出脉冲并具有时钟信号输出。
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公开(公告)号：US07466647B2
公开(公告)日：2008-12-16
申请号：US11054287
申请日：2005-02-09
申请人： Andrew James Bianchi , Eric Jason Fluhr , Masood Ahmed Khan , Michael Ju Hyeok Lee , Edelmar Seewann
发明人： Andrew James Bianchi , Eric Jason Fluhr , Masood Ahmed Khan , Michael Ju Hyeok Lee , Edelmar Seewann
CPC分类号： G06F13/4018 , G11C7/1006
摘要： A method and apparatus for using a 2:1 MUX to control read access, data bypass, and page size bypass in a memory array. The mechanism of the present invention reduces the 3:1 MUX normally required to manage these three functions to a 2:1 MUX.
摘要翻译： 一种使用2：1 MUX来控制存储器阵列中的读访问，数据旁路和页大小旁路的方法和装置。 本发明的机制将通常需要的3：1 MUX将这三个功能管理到2：1 MUX。
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25.发明授权Multifunctional latch circuit for use with both SRAM array and self test device 失效多功能锁存电路，用于SRAM阵列和自检装置公开(公告)号：US07099201B1
公开(公告)日：2006-08-29
申请号：US11055043
申请日：2005-02-10
申请人： Andrew James Bianchi , Yuen Hung Chan , William Vincent Huott , Michael Ju Hyeok Lee , Edelmar Seewann , Philip George Shephard, III
发明人： Andrew James Bianchi , Yuen Hung Chan , William Vincent Huott , Michael Ju Hyeok Lee , Edelmar Seewann , Philip George Shephard, III
IPC分类号： G11C7/10
CPC分类号： G11C29/1201 , G11C11/41 , G11C11/419 , G11C29/12
摘要： An apparatus and method is provided that combines both self test and functional features in a single latch circuit, which may be used with an SRAM array and is usefully embodied as an L1-L2 latch. During partial writes from an SRAM array, data bits of unknown state are inhibited from entering the latch circuit, while data for testing is allowed to enter. In one useful embodiment of the invention the latch circuit is used with a mode control that provides mode select signals to operate the latch circuit in one of a plurality of modes, including at least full write and partial write modes. The latch circuit further includes a data hold circuit for selectively receiving and storing data coupled to the latch circuit. A first enabling circuit responsive to the mode select signals enables the hold circuit to receive all the data contained in the array during a full write mode, and further enables the hold circuit to receive only some of the data bits contained in the array during a partial write mode.
摘要翻译： 提供了一种在单个锁存电路中组合自检和功能特征的装置和方法，其可以与SRAM阵列一起使用，并且被有效地实现为L1-L2锁存器。 在从SRAM阵列的部分写入期间，未知状态的数据位被禁止进入锁存电路，而用于测试的数据被允许进入。 在本发明的一个有用的实施例中，锁存电路与提供模式选择信号的模式控制一起使用，以便以至少全写和部分写模式的多种模式之一来操作锁存电路。 锁存电路还包括数据保持电路，用于选择性地接收和存储耦合到锁存电路的数据。 响应于模式选择信号的第一使能电路使得保持电路能够在完全写入模式期间接收包含在阵列中的所有数据，并且还允许保持电路仅在部分时钟期间仅接收阵列中包含的一些数据位 写模式。
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26.发明授权公开(公告)号：US06825691B1
公开(公告)日：2004-11-30
申请号：US10455163
申请日：2003-06-05
IPC分类号： H03K19173
CPC分类号： G11C11/4125
摘要： According to one form, a latch has an output node and sublatches. The sublatches each have an output node coupled to input circuitry and feedback circuitry coupled to the sublatch's output node for reinforcing an output signal of the sublatch. The sublatches are operable to receive a data signal at their respective input circuitry and to generate output signals on their respective output nodes. At least one sublatch output node is coupled to the latch output node. The output nodes of other ones of the sublatches are connected in the latch such that if any one of the sublatches is subjected to a radiation induced erroneous change of state the output signals of the other sublatches reduce an effect of the change on the latch output signal. The latch also includes a number of scanning-mode control switches coupled to ones of the sublatches for scanning data in or out.
摘要翻译： 根据一种形式，锁存器具有输出节点和副组。 这些副组件各自具有耦合到输入电路的输出节点和耦合到重叠器输出节点的反馈电路，用于加强子锁的输出信号。 这些集合可操作以在它们各自的输入电路处接收数据信号，并在它们各自的输出节点上产生输出信号。 至少一个子批输出节点耦合到锁存器输出节点。 其他的一些子实体的输出节点连接在锁存器中，使得如果任何一个子实体受到辐射引起的状态的错误改变，则其他子集合的输出信号会减小锁存器输出信号的变化的影响 。 锁存器还包括多个扫描模式控制开关，其耦合到用于扫描数据的一个或多个子集。
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公开(公告)号：US6052008A
公开(公告)日：2000-04-18
申请号：US892861
申请日：1997-07-14
IPC分类号： H03K19/096
CPC分类号： H03K19/0963
摘要： A logic circuit includes an inverter for generating a complement of an output signal from another logic circuit for input to a dynamic logic circuit. The dynamic logic circuit is capable of receiving both the complement signal and dynamic input signals during both the precharge and evaluate phases of the dynamic logic circuit. The complement signal is permitted to switch from both a low level to a high level and a high level to a low level during such stages with the dynamic logic circuit still capable of correctly evaluating the implemented logical operation of the dynamic logic circuit on the complement signal and the dynamic input signals. A p-channel FET is coupled between the internal precharge node and a voltage reference source where the gate electrode of the p-channel FET device receives the complement signal. Such a configuration eliminates the need for duplicate circuitry necessary to generate the complement signal for use by the dynamic logic circuit and also eliminates the addition of clock skew necessary to prevent potential false switching when using a complement signal generated by simple inversion.
摘要翻译： 逻辑电路包括用于产生来自另一逻辑电路的输出信号的补码以输入到动态逻辑电路的反相器。 在动态逻辑电路的预充电和评估阶段期间，动态逻辑电路能够接收补码信号和动态输入信号。 允许补码信号在这样的阶段期间从低电平切换到高电平和高电平，而动态逻辑电路仍然能够正确地评估动态逻辑电路在补码信号上的逻辑运算 和动态输入信号。 p沟道FET耦合在内部预充电节点和p型沟道FET器件的栅电极接收补码信号的电压参考源之间。 这种配置消除了生成用于由动态逻辑电路使用的补码信号所需的重复电路的需要，并且还消除了当使用由简单反演产生的补码信号时防止潜在的错开关所必需的时钟偏移的相加。
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公开(公告)号：US20100027361A1
公开(公告)日：2010-02-04
申请号：US12185234
申请日：2008-08-04
IPC分类号： G11C7/00
CPC分类号： G11C7/12 , G11C11/413
摘要： An information handling system (IHS) includes a processor with on-chip or off-chip SRAM array. After a read operation, a control circuit may instruct the SRAM array to conduct a precharge operation, or alternatively, instruct the SRAM array to conduct an equalize bitline voltage operation. A read operation may follow the precharge operation or the equalize bitline voltage operation. The control circuit may instruct the SRAM array to conduct an equalize bitline voltage operation if an equalized voltage of a bitline pair exhibits more that a predetermined amount of voltage. Otherwise, the control circuit instructs the SRAM array to conduct a precharge operation before the next read operation.
摘要翻译： 信息处理系统（IHS）包括具有片上或片外SRAM阵列的处理器。 在读取操作之后，控制电路可以指示SRAM阵列进行预充电操作，或者替代地指示SRAM阵列进行均衡的位线电压操作。 读取操作可以遵循预充电操作或均衡位线电压操作。 如果位线对的均衡电压显示出更多的预定量的电压，则控制电路可以指示SRAM阵列进行均衡的位线电压操作。 否则，控制电路指示SRAM阵列在下一次读取操作之前进行预充电操作。
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公开(公告)号：US20100002525A1
公开(公告)日：2010-01-07
申请号：US12166421
申请日：2008-07-02
CPC分类号： G11C7/1078 , G11C7/1087 , G11C7/1093 , G11C7/22
摘要： A data input latch and clocking method and apparatus for high performance SRAM in which an L1 data input latch is controlled by a logical combination of the normal local clock buffer clock signal and the local array clock buffer clock signal. This logical combination of clock signals minimizes the hold time of the L1 latch provides a fast cycle time in which the SRAM macro can process successive write instructions while avoiding early mode issues.
摘要翻译： 一种用于高性能SRAM的数据输入锁存和时钟方法和装置，其中L1数据输入锁存器由正常本地时钟缓冲时钟信号和本地阵列时钟缓冲时钟信号的逻辑组合控制。 时钟信号的这种逻辑组合使得L1锁存器的保持时间最小化提供了快速周期时间，其中SRAM宏可以处理连续写指令，同时避免早期模式问题。
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30.发明申请SYSTEM AND COMPUTER PROGRAM FOR VERIFYING PERFORMANCE OF AN ARRAY BY SIMULATING OPERATION OF EDGE CELLS IN A FULL ARRAY MODEL 有权通过模拟边缘细胞在全阵列模型中的操作来验证阵列性能的系统和计算机程序公开(公告)号：US20080270963A1
公开(公告)日：2008-10-30
申请号：US12166811
申请日：2008-07-02
IPC分类号： G06F17/50
CPC分类号： G06F17/5022
摘要： A system and computer program for verifying performance of an array by simulating operation of edge cells in a full array model reduces the computation time required for complete design verification. The edge cells of the array (or each subarray if the array is partitioned) are subjected to a timing simulation while the center cells of the array are logically disabled, but remain in the circuit model, providing proper loading. Additional cells are specified for simulation if calculations indicate a worst-case condition due to a non-edge cell. Wordline arrivals are observed to determine worst-case rows for selection. For write operations, the difference between the wordline edges and the data edges is used to locate any non-edge “outlier” cells. For read operations, the wordline delays are summed with the bitline delays determined from edge column data to locate any outliers.
摘要翻译： 通过模拟全阵列模型中边缘单元的操作来验证阵列的性能的系统和计算机程序减少了完整设计验证所需的计算时间。 阵列的边缘单元（或阵列分割的每个子阵列）经受定时仿真，而阵列的中心单元在逻辑上被禁用，但保留在电路模型中，从而提供适当的加载。 如果计算指示由于非边缘单元造成的最坏情况，则指定额外的单元用于模拟。 观察到字线到达以确定最坏情况行进行选择。 对于写入操作，字边和数据边之间的差异用于定位任何非边缘“异常值”单元。 对于读取操作，字线延迟与从边沿列数据确定的位线延迟相加以定位任何异常值。
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