公开(公告)号：US08304836B2

公开(公告)日：2012-11-06

申请号：US12620234

申请日：2009-11-17

申请人： Hemanth Jagannathan ,  Takashi Ando ,  Lisa F. Edge ,  Sufi Zafar ,  Changhwan Choi ,  Paul C. Jamison ,  Vamsi K. Paruchuri ,  Vijay Narayanan

发明人： Hemanth Jagannathan ,  Takashi Ando ,  Lisa F. Edge ,  Sufi Zafar ,  Changhwan Choi ,  Paul C. Jamison ,  Vamsi K. Paruchuri ,  Vijay Narayanan

IPC分类号： H01L21/70

CPC分类号： H01L29/42364 ,  H01L21/225 ,  H01L21/28088 ,  H01L21/28176 ,  H01L21/28185 ,  H01L21/324 ,  H01L21/477 ,  H01L21/823462 ,  H01L21/823835 ,  H01L21/823842 ,  H01L21/823857 ,  H01L29/1054 ,  H01L29/401 ,  H01L29/4958 ,  H01L29/4966 ,  H01L29/51 ,  H01L29/513 ,  H01L29/517

摘要： Equivalent oxide thickness (EOT) scaled high k/metal gate stacks are provided in which the capacitance bottleneck of the interfacial layer is substantially eliminated, with minimal compromise on the mobility of carriers in the channel of the device. In one embodiment, the aforementioned EOT scaled high k/metal gate stacks are achieved by increasing the dielectric constant of the interfacial layer to a value that is greater than the originally formed interfacial layer, i.e., the interfacial layer prior to diffusion of a high k material dopant element therein. In another embodiment, the aforementioned scaled high k/metal gate stacks are achieved by eliminating the interfacial layer from the structure. In yet another embodiment, the aforementioned high k/metal gate stacks are achieved by both increasing the dielectric constant of the interfacial layer and reducing/eliminating the interfacial layer.

摘要翻译： 提供了相当于氧化物厚度（EOT）的高k /金属栅极叠层，其中基本上消除了界面层的电容瓶颈，对器件沟道中载流子的迁移率的影响最小。 在一个实施例中，通过将界面层的介电常数提高到大于原始形成的界面层的值，即高k扩散之前的界面层，可实现上述EOT缩放的高k /金属栅极堆叠 材料掺杂元素。 在另一个实施例中，通过从结构中消除界面层来实现上述缩放的高k /金属栅极堆叠。 在另一个实施方案中，上述高k /金属栅极堆叠是通过增加界面层的介电常数和减少/消除界面层来实现的。

公开(公告)号：US20110115027A1

公开(公告)日：2011-05-19

申请号：US12620234

申请日：2009-11-17

申请人： Hemanth Jagannathan ,  Takashi Ando ,  Lisa F. Edge ,  Sufi Zafar ,  Changhwan Choi ,  Paul C. Jamison ,  Vamsi K. Paruchuri ,  Vijay Narayanan

发明人： Hemanth Jagannathan ,  Takashi Ando ,  Lisa F. Edge ,  Sufi Zafar ,  Changhwan Choi ,  Paul C. Jamison ,  Vamsi K. Paruchuri ,  Vijay Narayanan

IPC分类号： H01L27/092 ,  H01L29/78 ,  H01L21/8238 ,  H01L21/263

CPC分类号： H01L29/42364 ,  H01L21/225 ,  H01L21/28088 ,  H01L21/28176 ,  H01L21/28185 ,  H01L21/324 ,  H01L21/477 ,  H01L21/823462 ,  H01L21/823835 ,  H01L21/823842 ,  H01L21/823857 ,  H01L29/1054 ,  H01L29/401 ,  H01L29/4958 ,  H01L29/4966 ,  H01L29/51 ,  H01L29/513 ,  H01L29/517

摘要： Equivalent oxide thickness (EOT) scaled high k/metal gate stacks are provided in which the capacitance bottleneck of the interfacial layer is substantially eliminated, with minimal compromise on the mobility of carriers in the channel of the device. In one embodiment, the aforementioned EOT scaled high k/metal gate stacks are achieved by increasing the dielectric constant of the interfacial layer to a value that is greater than the originally formed interfacial layer, i.e., the interfacial layer prior to diffusion of a high k material dopant element therein. In another embodiment, the aforementioned scaled high k/metal gate stacks are achieved by eliminating the interfacial layer from the structure. In yet another embodiment, the aforementioned high k/metal gate stacks are achieved by both increasing the dielectric constant of the interfacial layer and reducing/eliminating the interfacial layer.

摘要翻译： 提供了相当于氧化物厚度（EOT）的高k /金属栅极叠层，其中基本上消除了界面层的电容瓶颈，对器件沟道中载流子的迁移率的影响最小。 在一个实施例中，通过将界面层的介电常数提高到大于原始形成的界面层的值，即高k扩散之前的界面层，可实现上述EOT缩放的高k /金属栅极堆叠 材料掺杂元素。 在另一个实施例中，通过从结构中消除界面层来实现上述缩放的高k /金属栅极堆叠。 在另一个实施方案中，上述高k /金属栅极堆叠是通过增加界面层的介电常数和减少/消除界面层来实现的。

公开(公告)号：US20090008725A1

公开(公告)日：2009-01-08

申请号：US11773160

申请日：2007-07-03

申请人： Supratik Guha ,  Fenton R. McFeely ,  Vijay Narayanan ,  Vamsi K. Paruchuri ,  John J. Yurkas

发明人： Supratik Guha ,  Fenton R. McFeely ,  Vijay Narayanan ,  Vamsi K. Paruchuri ,  John J. Yurkas

IPC分类号： H01L29/76 ,  H01L21/3205

CPC分类号： H01L21/28088 ,  H01L21/28194 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518

摘要： A method of forming an electropositive metal-containing capping layer atop a stack of a high k gate dielectric/interfacial layer that avoids chemically and physically altering the high k gate dielectric and the interfacial layer is provided. The method includes chemical vapor deposition of an electropositive metal-containing precursor at a temperature that is about 400° C. or less. The present invention also provides semiconductor structures such as, for example, MOSCAPs and MOSFETs, that include a chemical vapor deposited electropositive metal-containing capping layer atop a stack of a high k gate dielectric and an interfacial layer. The presence of the CVD electropositive metal-containing capping layer does not physically or chemically alter the high k gate dielectric and the interfacial layer.

公开(公告)号：US07067422B2

公开(公告)日：2006-06-27

申请号：US10830804

申请日：2004-03-31

申请人： Kazuhito Nakamura ,  Hideaki Yamasaki ,  Yumiko Kawano ,  Gert J. Leusink ,  Fenton R. McFeely ,  John J. Yurkas ,  Vijay Narayanan

发明人： Kazuhito Nakamura ,  Hideaki Yamasaki ,  Yumiko Kawano ,  Gert J. Leusink ,  Fenton R. McFeely ,  John J. Yurkas ,  Vijay Narayanan

IPC分类号： H01L21/44

CPC分类号： H01L21/28088 ,  H01L21/28194 ,  H01L29/4966 ,  H01L29/51 ,  H01L29/517

摘要： A method for forming a tantalum-containing gate electrode structure by providing a substrate having a high-k dielectric layer thereon in a process chamber and forming a tantalum-containing layer on the high-k dielectric layer in a thermal chemical vapor deposition process by exposing the substrate to a process gas containing TAIMATA (Ta(N(CH3)2)3(NC(C2H5)(CH3)2)) precursor gas. In one embodiment of the invention, the tantalum-containing layer can include a TaSiN layer formed from a process gas containing TAIMATA precursor gas, a silicon containing gas, and optionally a nitrogen-containing gas. In another embodiment of the invention, a TaN layer is formed on the TaSiN layer. The TaN layer can be formed from a process gas containing TAIMATA precursor gas and optionally a nitrogen-containing gas. A computer readable medium executable by a processor to cause a processing system to perform the method and a processing system for forming a tantalum-containing gate electrode structure are also provided.

摘要翻译： 一种通过在处理室中提供具有高k电介质层的衬底并在热化学气相沉积工艺中在高k电介质层上形成含钽层的方法来形成含钽栅电极结构的方法， 将衬底加工成含有TAIMATA（Ta（N（CH 3）2）3）（NC（C 2）2）的工艺气体， （CH 3）2））前体气体。 在本发明的一个实施方案中，含钽层可以包括由含有TAIMATA前体气体，含硅气体和任选的含氮气体的工艺气体形成的TaSiN层。 在本发明的另一实施例中，在TaSiN层上形成TaN层。 TaN层可以由含有TAIMATA前体气体和任选的含氮气体的工艺气体形成。 还提供了可由处理器执行以使处理系统执行该方法的计算机可读介质和用于形成含钽栅电极结构的处理系统。

公开(公告)号：US20090294876A1

公开(公告)日：2009-12-03

申请号：US12541241

申请日：2009-08-14

申请人： Supratik Guha ,  Fenton R. McFeely ,  Vijay Narayanan ,  Vamsi K. Paruchuri ,  John J. Yurkas

发明人： Supratik Guha ,  Fenton R. McFeely ,  Vijay Narayanan ,  Vamsi K. Paruchuri ,  John J. Yurkas

IPC分类号： H01L29/78

CPC分类号： H01L21/28088 ,  H01L21/28194 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518

摘要： A method of forming an electropositive metal-containing capping layer atop a stack of a high k gate dielectric/interfacial layer that avoids chemically and physically altering the high k gate dielectric and the interfacial layer is provided. The method includes chemical vapor deposition of an electropositive metal-containing precursor at a temperature that is about 400° C. or less. The present invention also provides semiconductor structures such as, for example, MOSCAPs and MOSFETs, that include a chemical vapor deposited electropositive metal-containing capping layer atop a stack of a high k gate dielectric and an interfacial layer. The presence of the CVD electropositive metal-containing capping layer does not physically or chemically alter the high k gate dielectric and the interfacial layer.

摘要翻译： 提供了一种在高k栅极电介质/界面层的堆叠顶上形成正电的含金属覆盖层的方法，其避免化学和物理改变高k栅极电介质和界面层。 该方法包括在约400℃或更低的温度下化学气相沉积含正电性金属的前体。 本发明还提供半导体结构，例如MOSCAP和MOSFET，其包括在高k栅极电介质和界面层的堆叠顶上的化学气相沉积的正电性含金属覆盖层。 CVD正电金属覆盖层的存在不会物理或化学地改变高k栅极电介质和界面层。

公开(公告)号：US07488656B2

公开(公告)日：2009-02-10

申请号：US11119310

申请日：2005-04-29

申请人： Eduard A. Cartier ,  Matthew W. Copel ,  Supratik Guha ,  Richard A. Haight ,  Fenton R. McFeely ,  Vijay Narayanan

发明人： Eduard A. Cartier ,  Matthew W. Copel ,  Supratik Guha ,  Richard A. Haight ,  Fenton R. McFeely ,  Vijay Narayanan

IPC分类号： H01L21/336

CPC分类号： H01L21/823462 ,  H01L21/28079 ,  H01L21/28088 ,  H01L21/28176 ,  H01L21/28194 ,  H01L21/31691 ,  H01L21/823842 ,  H01L21/823857 ,  H01L29/4958 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/7833

摘要： The present invention provides a method for removing charged defects from a material stack including a high k gate dielectric and a metal contact such that the final gate stack, which is useful in forming a pFET device, has a threshold voltage substantially within the silicon band gap and good carrier mobility. Specifically, the present invention provides a re-oxidation procedure that will restore the high k dielectric of a pFET device to its initial, low-defect state. It was unexpectedly determined that by exposing a material stack including a high k gate dielectric and a metal to dilute oxygen at low temperatures will substantially eliminate oxygen vacancies, resorting the device threshold to its proper value. Furthermore, it was determined that if dilute oxygen is used, it is possible to avoid undue oxidation of the underlying semiconductor substrate which would have a deleterious effect on the capacitance of the final metal-containing gate stack. The present invention also provides a semiconductor structure that includes at least one gate stack that has a threshold voltage within a control range and has good carrier mobility.

摘要翻译： 本发明提供了一种用于从包括高k栅极电介质和金属接触的材料堆叠中去除带电缺陷的方法，使得用于形成pFET器件的最终栅极堆叠具有基本上在硅带隙内的阈值电压 和良好的载波移动性。 具体地说，本发明提供了将pFET器件的高k电介质恢复到其初始低缺陷状态的再氧化过程。 意外地确定，通过暴露包括高k栅极电介质和金属的材料堆以在低温下稀释氧将基本上消除氧空位，使装置阈值达到适当的值。 此外，确定如果使用稀释氧，则可以避免对最终含金属的栅极叠层的电容产生有害影响的下面的半导体衬底的不适当的氧化。 本发明还提供一种半导体结构，该半导体结构包括至少一个栅极堆叠，其具有在控制范围内的阈值电压并具有良好的载流子迁移率。

公开(公告)号：US08193051B2

公开(公告)日：2012-06-05

申请号：US13047172

申请日：2011-03-14

申请人： Nestor A. Bojarczuk, Jr. ,  Cyril Cabral, Jr. ,  Eduard A. Cartier ,  Matthew W. Copel ,  Martin M. Frank ,  Evgeni P. Gousev ,  Supratik Guha ,  Rajarao Jammy ,  Vijay Narayanan ,  Vamsi K. Paruchuri

发明人： Nestor A. Bojarczuk, Jr. ,  Cyril Cabral, Jr. ,  Eduard A. Cartier ,  Matthew W. Copel ,  Martin M. Frank ,  Evgeni P. Gousev ,  Supratik Guha ,  Rajarao Jammy ,  Vijay Narayanan ,  Vamsi K. Paruchuri

IPC分类号： H01L21/8238

CPC分类号： H01L29/513 ,  H01L21/28079 ,  H01L21/28088 ,  H01L21/823857 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/517

摘要： The present invention provides a semiconductor structure including a semiconductor substrate having a plurality of source and drain diffusion regions located therein, each pair of source and drain diffusion regions are separated by a device channel. The structure further includes a first gate stack of pFET device located on top of some of the device channels, the first gate stack including a high-k gate dielectric, an insulating interlayer abutting the gate dielectric and a fully silicided metal gate electrode abutting the insulating interlayer, the insulating interlayer includes an insulating metal nitride that stabilizes threshold voltage and flatband voltage of the p-FET device to a targeted value and is one of aluminum oxynitride, boron nitride, boron oxynitride, gallium nitride, gallium oxynitride, indium nitride and indium oxynitride. A second gate stack of an nFET devices is located on top remaining device channels, the second gate stack including a high-k gate dielectric and a fully silicided gate electrode located directly atop the high-k gate dielectric.

摘要翻译： 本发明提供一种半导体结构，其包括具有位于其中的多个源极和漏极扩散区域的半导体衬底，每对源极和漏极扩散区域由器件沟道分离。 该结构还包括位于一些器件通道顶部的pFET器件的第一栅极堆叠，第一栅极堆叠包括高k栅极电介质，邻接栅极电介质的绝缘夹层和邻接绝缘体的完全硅化金属栅电极 中间层，绝缘中间层包括将p-FET器件的阈值电压和扁平带电压稳定到目标值的绝缘金属氮化物，并且是氮氧化铝，氮化硼，氮氧化硼，氮化镓，氮氧化镓，氮化铟和铟中的一种 氮氧化物。 nFET器件的第二栅极堆叠位于顶部剩余器件沟道上，第二栅极堆叠包括高k栅极电介质和直接位于高k栅极电介质顶部的完全硅化栅电极。

公开(公告)号：US07928514B2

公开(公告)日：2011-04-19

申请号：US12355368

申请日：2009-01-16

申请人： Nestor A. Bojarczuk, Jr. ,  Cyril Cabral, Jr. ,  Eduard A. Cartier ,  Matthew W. Copel ,  Martin M. Frank ,  Evgeni P. Gousev ,  Supratik Guha ,  Rajarao Jammy ,  Vijay Narayanan ,  Vamsi K. Paruchuri

发明人： Nestor A. Bojarczuk, Jr. ,  Cyril Cabral, Jr. ,  Eduard A. Cartier ,  Matthew W. Copel ,  Martin M. Frank ,  Evgeni P. Gousev ,  Supratik Guha ,  Rajarao Jammy ,  Vijay Narayanan ,  Vamsi K. Paruchuri

IPC分类号： H01L29/76

CPC分类号： H01L29/513 ,  H01L21/28079 ,  H01L21/28088 ,  H01L21/823857 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/517

摘要： The present invention provides a semiconductor structure including a semiconductor substrate having a plurality of source and drain diffusion regions located therein, each pair of source and drain diffusion regions are separated by a device channel. The structure further includes a first gate stack of pFET device located on top of some of the device channels, the first gate stack including a high-k gate dielectric, an insulating interlayer abutting the gate dielectric and a fully silicided metal gate electrode abutting the insulating interlayer, the insulating interlayer includes an insulating metal nitride that stabilizes threshold voltage and flatband voltage of the p-FET device to a targeted value and is one of aluminum oxynitride, boron nitride, boron oxynitride, gallium nitride, gallium oxynitride, indium nitride and indium oxynitride. A second gate stack of an nFET devices is located on top remaining device channels, the second gate stack including a high-k gate dielectric and a fully silicided gate electrode located directly atop the high-k gate dielectric.

摘要翻译： 本发明提供一种半导体结构，其包括具有位于其中的多个源极和漏极扩散区域的半导体衬底，每对源极和漏极扩散区域由器件沟道分离。 该结构还包括位于一些器件通道顶部的pFET器件的第一栅极堆叠，第一栅极堆叠包括高k栅极电介质，邻接栅极电介质的绝缘夹层和邻接绝缘体的完全硅化金属栅电极 中间层，绝缘中间层包括将p-FET器件的阈值电压和扁平带电压稳定到目标值的绝缘金属氮化物，并且是氮氧化铝，氮化硼，氮氧化硼，氮化镓，氮氧化镓，氮化铟和铟中的一种 氮氧化物。 nFET器件的第二栅极堆叠位于顶部剩余器件沟道上，第二栅极堆叠包括高k栅极电介质和直接位于高k栅极电介质顶部的完全硅化栅电极。

公开(公告)号：US07785999B2

公开(公告)日：2010-08-31

申请号：US11830277

申请日：2007-07-30

申请人： Cyril Cabral, Jr. ,  Chester T. Dziobkowski ,  Sunfei Fang ,  Evgeni Gousev ,  Rajarao Jammy ,  Vijay Narayanan ,  Vamsi Paruchuri ,  Ghavam G. Shahidi ,  Michelle L. Steen ,  Clement H. Wann

发明人： Cyril Cabral, Jr. ,  Chester T. Dziobkowski ,  Sunfei Fang ,  Evgeni Gousev ,  Rajarao Jammy ,  Vijay Narayanan ,  Vamsi Paruchuri ,  Ghavam G. Shahidi ,  Michelle L. Steen ,  Clement H. Wann

IPC分类号： H01L21/44 ,  H01L21/8242

CPC分类号： H01L29/66507 ,  H01L21/28097 ,  H01L21/823443 ,  H01L29/66545

摘要： An advanced gate structure that includes a fully silicided metal gate and silicided source and drain regions in which the fully silicided metal gate has a thickness that is greater than the thickness of the silicided source/drain regions is provided. A method of forming the advanced gate structure is also provided in which the silicided source and drain regions are formed prior to formation of the silicided metal gate region.

摘要翻译： 提供了一种先进的栅极结构，其包括完全硅化金属栅极和硅化物源极和漏极区域，其中完全硅化金属栅极的厚度大于硅化物源极/漏极区域的厚度。 还提供了形成高级栅极结构的方法，其中在形成硅化金属栅极区之前形成硅化源极和漏极区。

公开(公告)号：US07271455B2

公开(公告)日：2007-09-18

申请号：US10890753

申请日：2004-07-14

申请人： Cyril Cabral, Jr. ,  Chester T. Dziobkowski ,  Sunfei Fang ,  Evgeni Gousev ,  Rajarao Jammy ,  Vijay Narayanan ,  Vamsi Paruchuri ,  Ghavam G. Shahidi ,  Michelle L. Steen ,  Clement H. Wann

发明人： Cyril Cabral, Jr. ,  Chester T. Dziobkowski ,  Sunfei Fang ,  Evgeni Gousev ,  Rajarao Jammy ,  Vijay Narayanan ,  Vamsi Paruchuri ,  Ghavam G. Shahidi ,  Michelle L. Steen ,  Clement H. Wann

IPC分类号： H01L21/336 ,  H01L29/76

CPC分类号： H01L29/66507 ,  H01L21/28097 ,  H01L21/823443 ,  H01L29/66545

摘要： An advanced gate structure that includes a fully silicided metal gate and silicided source and drain regions in which the fully silicided metal gate has a thickness that is greater than the thickness of the silicided source/drain regions is provided. A method of forming the advanced gate structure is also provided in which the silicided source and drain regions are formed prior to formation of the silicided metal gate region.

摘要翻译： 提供了一种先进的栅极结构，其包括完全硅化金属栅极和硅化物源极和漏极区域，其中完全硅化金属栅极的厚度大于硅化物源极/漏极区域的厚度。 还提供了形成高级栅极结构的方法，其中在形成硅化金属栅极区之前形成硅化源极和漏极区。