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公开(公告)号：US20170220510A1
公开(公告)日：2017-08-03
申请号：US15418497
申请日：2017-01-27
Applicant: D-Wave Systems Inc.
Inventor： Jeremy P. Hilton , Aidan Patrick Roy , Paul I. Bunyk , Andrew Douglas King , Tomas J. Boothby , Richard G. Harris , Chunqing Deng
CPC classification number: G06F13/4068 , G06F13/36 , G06N99/002
Abstract: Topologies for analog computing systems are provided. Qubits in the topology are grouped into cells, and cells are coupled to adjacent cells by inter-cell couplers. At least some cells are coupled to non-adjacent cells via long-range couplers. Long-range couplers may be arranged into coverings so that certain sets of qubits within a covering region may be coupled with a reduced number of couplers. Each cell within a covering region without a long-range coupler may be proximate to a cell with a long range coupler so that each cell within the covering region is no more than a certain coupling distance away from a long-range coupler. Long-range couplers may couple over a greater physical distance than inter-cell couplers. Long-range couplers may couple to qubits over a larger coupling region, and may extend across multiple crossing regions between qubits.
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公开(公告)号：US09710758B2
公开(公告)日：2017-07-18
申请号：US14691268
申请日：2015-04-20
Applicant: D-Wave Systems Inc.
Inventor： Paul I. Bunyk , Mohammad H. S. Amin , Richard G. Harris , Trevor Michael Lanting , Mark W. Johnson , Jeremy P. Hilton , Emile M. Hoskinson
CPC classification number: G06N99/002 , G06F15/82
Abstract: In a quantum processor some couplers couple a given qubit to a nearest neighbor qubit (e.g., vertically and horizontally in an ordered 2D array), other couplers couple to next-nearest neighbor qubits (e.g., diagonally in the ordered 2D array). Couplers may include half-couplers, to selectively provide communicative coupling between a given qubit and other qubits, which may or may not be nearest or even next-nearest-neighbors. Tunable couplers selective mediate communicative coupling. A control system may impose a connectivity on a quantum processor, different than an “as designed” or “as manufactured” physical connectivity. Imposition may be via a digital processor processing a working or updated working graph, to map or embed a problem graph. A set of exclude qubits may be created from a comparison of hardware and working graphs. An annealing schedule may adjust a respective normalized inductance of one or more qubits, for instance to exclude certain qubits.
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23.发明授权公开(公告)号：US11730066B2
公开(公告)日：2023-08-15
申请号：US17399375
申请日：2021-08-11
Applicant: D-WAVE SYSTEMS INC.
Inventor： Mark W. Johnson , Paul I. Bunyk , Andrew J. Berkley , Richard G. Harris , Kelly T. R. Boothby , Loren J. Swenson , Emile M. Hoskinson , Christopher B. Rich , Jan E. S. Johansson
CPC classification number: H10N60/124 , G06N10/00 , H10N60/805
Abstract: Approaches useful to operation of scalable processors with ever larger numbers of logic devices (e.g., qubits) advantageously take advantage of QFPs, for example to implement shift registers, multiplexers (i.e., MUXs), de-multiplexers (i.e., DEMUXs), and permanent magnetic memories (i.e., PMMs), and the like, and/or employ XY or XYZ addressing schemes, and/or employ control lines that extend in a “braided” pattern across an array of devices. Many of these described approaches are particularly suited for implementing input to and/or output from such processors. Superconducting quantum processors comprising superconducting digital-analog converters (DACs) are provided. The DACs may use kinetic inductance to store energy via thin-film superconducting materials and/or series of Josephson junctions, and may use single-loop or multi-loop designs. Particular constructions of energy storage elements are disclosed, including meandering structures. Galvanic connections between DACs and/or with target devices are disclosed, as well as inductive connections.
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公开(公告)号：US20230027682A1
公开(公告)日：2023-01-26
申请号：US17786192
申请日：2020-12-15
Applicant: D-WAVE SYSTEMS INC.
Inventor： Reza Molavi , Mark H. Volkmann , Emile M. Hoskinson , Richard G. Harris , Trevor M. Lanting , Paul I. Bunyk , Andrew J. Berkley
Abstract: An analog computing system having a qubit which is provided with inductors positioned near to the qubit's Josephson junctions and inductors positioned far from the qubit's Josephson junctions. The near inductors exhibit capacitance-reducing behavior and the far inductors exhibit capacitance-increasing behavior as their respective inductances are increased. Near and far inductors can be tuned to homogenize the capacitance of the qubit across a range of programmable states based on predicted and target capacitance for the qubit. The inductors may be tuned to homogenize both capacitance and inductance.
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公开(公告)号：US11526463B2
公开(公告)日：2022-12-13
申请号：US17355458
申请日：2021-06-23
Applicant: D-WAVE SYSTEMS INC.
Inventor： Alexander Maassen van den Brink , Peter Love , Mohammad H. S. Amin , Geordie Rose , David Grant , Miles F. H. Steininger , Paul I. Bunyk , Andrew J. Berkley
Abstract: Analog processors for solving various computational problems are provided. Such analog processors comprise a plurality of quantum devices, arranged in a lattice, together with a plurality of coupling devices. The analog processors further comprise bias control systems each configured to apply a local effective bias on a corresponding quantum device. A set of coupling devices in the plurality of coupling devices is configured to couple nearest-neighbor quantum devices in the lattice. Another set of coupling devices is configured to couple next-nearest neighbor quantum devices. The analog processors further comprise a plurality of coupling control systems each configured to tune the coupling value of a corresponding coupling device in the plurality of coupling devices to a coupling. Such quantum processors further comprise a set of readout devices each configured to measure the information from a corresponding quantum device in the plurality of quantum devices.
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Patent Agency Ranking
公开(公告)号：US11031537B2
公开(公告)日：2021-06-08
申请号：US16380751
申请日：2019-04-10
Applicant: D-WAVE SYSTEMS INC.
Inventor： Richard G. Harris , Andrew J. Berkley , Jan Johansson , Mark Johnson , Mohammad Amin , Paul I. Bunyk
Abstract: Apparatus and methods enable active compensation for unwanted discrepancies in the superconducting elements of a quantum processor. A qubit may include a primary compound Josephson junction (CJJ) structure, which may include at least a first secondary CJJ structure to enable compensation for Josephson junction asymmetry in the primary CJJ structure. A qubit may include a series LC-circuit coupled in parallel with a first CJJ structure to provide a tunable capacitance. A qubit control system may include means for tuning inductance of a qubit loop, for instance a tunable coupler inductively coupled to the qubit loop and controlled by a programming interface, or a CJJ structure coupled in series with the qubit loop and controlled by a programming interface.
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公开(公告)号：US20200293486A1
公开(公告)日：2020-09-17
申请号：US16859672
申请日：2020-04-27
Applicant: D-WAVE SYSTEMS INC.
Inventor： Alexander Maassen van den Brink , Peter Love , Mohammad H.S. Amin , Geordie Rose , David Grant , Miles F.H. Steininger , Paul I. Bunyk , Andrew J. Berkley
Abstract: Analog processors for solving various computational problems are provided. Such analog processors comprise a plurality of quantum devices, arranged in a lattice, together with a plurality of coupling devices. The analog processors further comprise bias control systems each configured to apply a local effective bias on a corresponding quantum device. A set of coupling devices in the plurality of coupling devices is configured to couple nearest-neighbor quantum devices in the lattice. Another set of coupling devices is configured to couple next-nearest neighbor quantum devices. The analog processors further comprise a plurality of coupling control systems each configured to tune the coupling value of a corresponding coupling device in the plurality of coupling devices to a coupling. Such quantum processors further comprise a set of readout devices each configured to measure the information from a corresponding quantum device in the plurality of quantum devices.
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公开(公告)号：US20200274050A1
公开(公告)日：2020-08-27
申请号：US16870537
申请日：2020-05-08
Applicant: D-WAVE SYSTEMS INC.
Inventor： Eric Ladizinsky , Jeremy P. Hilton , Byong Hyop Oh , Paul I. Bunyk
IPC: H01L39/24 , B82Y10/00 , H01L27/18 , H01L39/22 , H01L21/285 , H01L21/768 , H01L39/02 , H01L39/12
Abstract: Various techniques and apparatus permit fabrication of superconductive circuits. A niobium/aluminum oxide/niobium trilayer may be formed and individual Josephson Junctions (JJs) formed. A protective cap may protect a JJ during fabrication. A hybrid dielectric may be formed. A superconductive integrated circuit may be formed using a subtractive patterning and/or additive patterning. A superconducting metal layer may be deposited by electroplating and/or polished by chemical-mechanical planarization. The thickness of an inner layer dielectric may be controlled by a deposition process. A substrate may include a base of silicon and top layer including aluminum oxide. Depositing of superconducting metal layer may be stopped or paused to allow cooling before completion. Multiple layers may be aligned by patterning an alignment marker in a superconducting metal layer.
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公开(公告)号：US20190324941A1
公开(公告)日：2019-10-24
申请号：US16421211
申请日：2019-05-23
Applicant: D-WAVE SYSTEMS INC.
Inventor： Alexander Maassen van den Brink , Peter Love , Mohammad H.S. Amin , Geordie Rose , David Grant , Miles F.H. Steininger , Paul I. Bunyk , Andrew J. Berkley
Abstract: Analog processors for solving various computational problems are provided. Such analog processors comprise a plurality of quantum devices, arranged in a lattice, together with a plurality of coupling devices. The analog processors further comprise bias control systems each configured to apply a local effective bias on a corresponding quantum device. A set of coupling devices in the plurality of coupling devices is configured to couple nearest-neighbor quantum devices in the lattice. Another set of coupling devices is configured to couple next-nearest neighbor quantum devices. The analog processors further comprise a plurality of coupling control systems each configured to tune the coupling value of a corresponding coupling device in the plurality of coupling devices to a coupling. Such quantum processors further comprise a set of readout devices each configured to measure the information from a corresponding quantum device in the plurality of quantum devices.
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公开(公告)号：US20190228331A1
公开(公告)日：2019-07-25
申请号：US16258082
申请日：2019-01-25
Applicant: D-WAVE SYSTEMS INC.
Inventor： Richard G. Harris , Paul I. Bunyk , Mohammad H.S. Amin , Emile M. Hoskinson
Abstract: In a quantum processor some couplers couple a given qubit to a nearest neighbor qubit (e.g., vertically and horizontally in an ordered 2D array), other couplers couple to next-nearest neighbor qubits (e.g., diagonally in the ordered 2D array). Couplers may include half-couplers, to selectively provide communicative coupling between a given qubit and other qubits, which may or may not be nearest or even next-nearest-neighbors. Tunable couplers selective mediate communicative coupling. A control system may impose a connectivity on a quantum processor, different than an “as designed” or “as manufactured” physical connectivity. Imposition may be via a digital processor processing a working or updated working graph, to map or embed a problem graph. A set of exclude qubits may be created from a comparison of hardware and working graphs. An annealing schedule may adjust a respective normalized inductance of one or more qubits, for instance to exclude certain qubits.
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