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21.发明申请公开(公告)号：US20120081873A1
公开(公告)日：2012-04-05
申请号：US12895251
申请日：2010-09-30
CPC分类号： H05K3/4623 , H05K1/0216 , H05K1/141 , H05K3/368 , H05K2201/10189 , Y10T29/49126 , Y10T29/49162 , Y10T29/53004
摘要： Some embodiments of the inventive subject matter are directed to a first circuit board configured to include an electronic component. The electronic component includes a plurality of leads. The first circuit board includes first wires configured to connect to a first portion of the plurality of leads. The second circuit board is affixed to the first circuit board. The second circuit board includes second wires. The second circuit board is smaller in size than the first circuit board. A plurality of electrical connectors extend through a thickness of the first circuit board and are configured to connect a second portion of the plurality of leads to the second wires.
摘要翻译： 本发明的一些实施例涉及被配置为包括电子部件的第一电路板。 电子部件包括多个引线。 第一电路板包括被配置为连接到多个引线的第一部分的第一布线。 第二电路板固定在第一电路板上。 第二电路板包括第二导线。 第二个电路板的尺寸比第一个电路板小。 多个电连接器延伸穿过第一电路板的厚度，并且被配置为将多个引线的第二部分连接到第二导线。
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22.发明授权Physical interface macros (PHYS) supporting heterogeneous electrical properties 失效物理接口宏（PHYS）支持异质电气特性公开(公告)号：US08051228B2
公开(公告)日：2011-11-01
申请号：US12270576
申请日：2008-11-13
CPC分类号： G06F13/4022 , G06F13/4072 , G06F2213/0026 , G06F2213/0028 , Y02D10/14 , Y02D10/151
摘要： An integrated processor design includes physical interface macros supporting heterogeneous electrical properties. The processor design comprises a plurality of processing cores and a plurality of physical interfaces to connect to a memory interface, a peripheral component interconnect express (PCI Express or PCIe) interface for input/output, an Ethernet interface for network communication, and/or a serial attached SCSI (SAS) interface for storage.
摘要翻译： 集成处理器设计包括支持异质电气特性的物理接口宏。 处理器设计包括多个处理核心和多个物理接口以连接到存储器接口，用于输入/输出的外围组件互连快速（PCI Express或PCIe）接口，用于网络通信的以太网接口和/或 串行连接SCSI（SAS）接口进行存储。
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公开(公告)号：US08018837B2
公开(公告)日：2011-09-13
申请号：US12635121
申请日：2009-12-10
IPC分类号： G01R31/08
CPC分类号： H01L22/22 , H01L2924/0002 , H01L2924/00
摘要： A method, apparatus, and computer instructions for managing a set of signal paths for a chip. A defective signal path within the set of signal paths for the chip is detected. Signals are re-routed through the set of signal paths such that the defective signal path is removed from the set of signal paths and sending signals using remaining data signal paths in the set of signal paths and using an extra signal path in response to detecting the defective signal path.
摘要翻译： 一种用于管理用于芯片的一组信号路径的方法，装置和计算机指令。 检测用于芯片的信号路径集合内的有缺陷的信号路径。 信号通过一组信号路径重新路由，使得有缺陷的信号路径从信号路径集合中移除，并使用信号路径组中的剩余数据信号路径发送信号，并且响应于检测到的信号路径 有缺陷的信号路径。
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公开(公告)号：US08004335B2
公开(公告)日：2011-08-23
申请号：US12028973
申请日：2008-02-11
IPC分类号： H03H11/16
CPC分类号： H03K5/15026 , H03B27/00 , H03H7/21 , H03H11/22 , H03K5/13 , H03K2005/00052 , H03K2005/00065 , H03K2005/00293
摘要： A phase interpolator system is disclosed that may include a clock to provide a clock signal, and a control section in communication with the clock to regulate the strength of the clock signal. The system may also include a generator circuit to produce an alternate clock signal based upon the strength of the clock signal received from the control section.
摘要翻译： 公开了可以包括提供时钟信号的时钟以及与时钟通信以调节时钟信号的强度的控制部分的相位内插器系统。 该系统还可以包括发电机电路，以根据从控制部分接收的时钟信号的强度来产生替代时钟信号。
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公开(公告)号：US07895374B2
公开(公告)日：2011-02-22
申请号：US12165809
申请日：2008-07-01
CPC分类号： G06F13/4243 , G06F11/2007 , G06F11/2017 , Y02D10/14 , Y02D10/151
摘要： A communication interface device, system, method, and design structure for providing dynamic segment sparing and repair in a memory system. The communication interface device includes drive-side switching logic including driver multiplexers to select driver data for transmitting on link segments of a bus, and receive-side switching logic including receiver multiplexers to select received data from the link segments of the bus. The bus includes multiple data link segments, a clock link segment, and at least two spare link segments selectable by the drive-side switching logic and the receive-side switching logic to replace one or more of the data link segments and the clock link segment.
摘要翻译： 用于在存储器系统中提供动态段保存和修复的通信接口设备，系统，方法和设计结构。 通信接口装置包括驱动侧切换逻辑，包括驱动器多路复用器，用于选择用于在总线的链路段上发送的驱动器数据，以及包括接收机多路复用器的接收侧切换逻辑，以从总线的链路段选择接收的数据。 该总线包括多个数据链路段，一个时钟链路段，以及由驱动器侧切换逻辑和接收侧切换逻辑选择的至少两个备用链路段，用于替换一个或多个数据链路段和时钟链路段 。
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26.发明申请公开(公告)号：US20100220536A1
公开(公告)日：2010-09-02
申请号：US12394804
申请日：2009-02-27
申请人： Paul W. Coteus , Daniel M. Dreps , Kevin C. Gower , Hillery C. Hunter , Charles A. Kilmer , Kyu-hyoun Kim , Kenneth L. Wright
发明人： Paul W. Coteus , Daniel M. Dreps , Kevin C. Gower , Hillery C. Hunter , Charles A. Kilmer , Kyu-hyoun Kim , Kenneth L. Wright
CPC分类号： G11C7/22 , G06F13/1689 , G11C7/1051 , G11C7/1057 , G11C7/106 , G11C7/1066 , G11C7/222 , G11C8/12 , Y02D10/14
摘要： A memory device including a memory array storing data, a variable delay controller, a passive variable delay circuit and an output driver. The variable delay controller periodically receives delay commands from a first source external to the memory device during operation of the memory device, and outputs delay instruction bits responsive to the received delay commands. The passive variable delay circuit receives a clock from a second source external to the memory device, receives the delay instruction bits from the variable delay controller, generates a delayed clock having a time relation to the received clock as determined by the delay instruction bits, and outputting the delayed clock. The output driver receives the data from the memory array and the delayed clock, and outputs the data at a time responsive to the delayed clock.
摘要翻译： 一种包括存储数据的存储器阵列，可变延迟控制器，无源可变延迟电路和输出驱动器的存储器件。 可变延迟控制器在存储器件的操作期间周期性地从存储器件外部的第一源接收延迟命令，并且响应于接收的延迟命令而输出延迟指令位。 无源可变延迟电路从存储器件外部的第二源接收时钟，从可变延迟控制器接收延迟指令位，产生与由延迟指令位确定的接收时钟具有时间关系的延迟时钟，以及 输出延迟时钟。 输出驱动器从存储器阵列和延迟时钟接收数据，并且响应于延迟的时钟一次输出数据。
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27.发明申请Method and Apparatus for Supporting Multiple High Bandwidth I/O Controllers on a Single Chip 有权在单芯片上支持多个高带宽I / O控制器的方法和装置公开(公告)号：US20100122011A1
公开(公告)日：2010-05-13
申请号：US12270569
申请日：2008-11-13
IPC分类号： G06F13/00
CPC分类号： G06F13/385
摘要： An integrated processor design includes physical interface macros supporting heterogeneous electrical properties. The processor design comprises a plurality of processing cores and a plurality of physical interfaces to connect to a memory interface, a peripheral component interconnect express (PCI Express or PCIe) interface for input/output, an Ethernet interface for network communication, and/or a serial attached SCSI (SAS) interface for storage. Each physical interface may be programmatically connected to a selected interface controller, such as a memory controller, a PCI Express controller, or an Ethernet controller, for example. A plurality of such controllers may be connected to a switch within the processor design, with the switch also being connected to each physical interface macro. Thus, the physical interface macros may be programmatically connected to a subset of the plurality of controllers.
摘要翻译： 集成处理器设计包括支持异质电气特性的物理接口宏。 处理器设计包括多个处理核心和多个物理接口以连接到存储器接口，用于输入/输出的外围组件互连快速（PCI Express或PCIe）接口，用于网络通信的以太网接口和/或 串行连接SCSI（SAS）接口进行存储。 每个物理接口可以以编程方式连接到例如存储器控制器，PCI Express控制器或以太网控制器等所选择的接口控制器。 多个这样的控制器可以连接到处理器设计中的开关，开关也连接到每个物理接口宏。 因此，物理接口宏可以以编程方式连接到多个控制器的子集。
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公开(公告)号：US20100005345A1
公开(公告)日：2010-01-07
申请号：US12165799
申请日：2008-07-01
IPC分类号： G06F11/00
CPC分类号： G06F11/167 , G06F11/073 , G06F11/076 , G06F11/1004 , G06F11/2007 , G11C5/04 , G11C29/02 , G11C29/022
摘要： A communication interface device, system, method, and design structure for bit shadowing in a memory system are provided. The communication interface device includes shadow selection logic to select a driver bit position as a shadowed driver value, and line drivers to transmit data for the selected driver bit position and the shadowed driver value on separate link segments of a bus. The communication interface device also includes shadow compare logic to compare a selected received value with a shadowed received value from the bus and identify a miscompare in response to a mismatch of the compare, and shadow counters to count a rate of the miscompare relative to a bus error rate over a period of time. A defective link segment is identified in response to the rate of the miscompare within a predefined threshold of the bus error rate.
摘要翻译： 提供了一种用于存储器系统中的位阴影的通信接口设备，系统，方法和设计结构。 通信接口设备包括用于选择驱动器位位置作为阴影驱动器值的阴影选择逻辑，以及线驱动器，以在总线的单独链路段上传送所选择的驱动器位位置和阴影驱动器值的数据。 通信接口设备还包括阴影比较逻辑，以将所选择的接收值与来自总线的阴影接收值进行比较，并且识别响应于比较不匹配的错误比较，以及阴影计数器来计数相对于总线的误比率 错误率在一段时间内。 响应于在总线错误率的预定阈值内的错误比较的速率来识别有缺陷的链路段。
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公开(公告)号：US07461287B2
公开(公告)日：2008-12-02
申请号：US11055866
申请日：2005-02-11
摘要： A mechanism for de-skewing and aligning data bits sent between two chips on an elastic interface. On the receiving end of an elastic interface, the eye of each data bit within a clock/data group is delayed by less than a bit time to align the eyes with the nearest clock edge of a received clock signal. In addition to aligning the eyes of the individual data bits with the nearest clock edge, IAP patterns are used to determine the amount of further delay needed to line up the individual data beats from each data bit. If the data beats for the data bits are not aligned, all but the slowest data beat are delayed to align the data beats for all bits. The additional delay is achieved using sample latches that result in a delayed signal with less jitter. As a result of having less jitter, the received, de-skewed, and aligned clock/data group can be forwarded to the operative portion of the receiving chip at an increased frequency.
摘要翻译： 用于在弹性界面上在两个芯片之间发送的数据位的偏斜和对准的机制。 在弹性接口的接收端，时钟/数据组内的每个数据位的眼睛被延迟小于一点时间，以使眼睛与接收到的时钟信号的最近的时钟沿对齐。 除了将各个数据位的眼睛与最近的时钟边沿对齐之外，还使用IAP模式来确定从每个数据位排列各个数据节拍所需的进一步延迟量。 如果数据位的数据跳转不对齐，除了最慢的数据跳转之外，除了所有位的数据跳转之外，都会被延迟。 使用采样锁存器实现额外的延迟，导致延迟信号抖动较小。 由于具有较少的抖动，所接收的，去偏斜的和对准的时钟/数据组可以以增加的频率转发到接收芯片的操作部分。
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公开(公告)号：US20080285697A1
公开(公告)日：2008-11-20
申请号：US11749409
申请日：2007-05-16
申请人： Kyu-hyoun Kim , Paul W. Coteus , Daniel M. Dreps
发明人： Kyu-hyoun Kim , Paul W. Coteus , Daniel M. Dreps
IPC分类号： H03D3/24
CPC分类号： H03K5/151 , H03K5/13 , H03K2005/00052 , H03K2005/00234
摘要： A system for providing open-loop quadrature clock generation. The system is implemented by a ring oscillator structure that includes input inverters for receiving an input clock, forward direction loop inverters, backward direction loop inverters, one or more outputs, and cross-coupled latches connected between any two opposite nodes.
摘要翻译： 一种用于提供开环正交时钟生成的系统。 该系统由环形振荡器结构实现，该环形振荡器结构包括用于接收输入时钟的输入反相器，正向环路逆变器，反向环路逆变器，一个或多个输出以及连接在任何两个相对节点之间的交叉耦合的锁存器。
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