MAINTAINING SYSTEM FIRMWARE IMAGES REMOTELY USING A DISTRIBUTE FILE SYSTEM PROTOCOL
    23.
    发明申请
    MAINTAINING SYSTEM FIRMWARE IMAGES REMOTELY USING A DISTRIBUTE FILE SYSTEM PROTOCOL 有权
    使用分布式文件系统协议远程维护系统固件映像

    公开(公告)号:US20140372560A1

    公开(公告)日:2014-12-18

    申请号:US14369760

    申请日:2012-02-21

    IPC分类号: H04L29/08 G06F9/445

    摘要: Maintaining system firmware images remotely using a distributed file system protocol is described. A method of preserving a system firmware image on a computer includes identifying that system firmware on the computer is to be updated with a new image, identifying an original image of the system firmware using a management processor of the computer, establishing a network connection to a remote storage system through a network interface of the computer using the management processor, sending the original image through the network connection to the remote storage system using a distributed file system protocol.

    摘要翻译: 描述使用分布式文件系统协议远程维护系统固件映像。 一种在计算机上保存系统固件图像的方法包括识别计算机上的系统固件将被更新为新图像,使用计算机的管理处理器识别系统固件的原始图像,建立到计算机的网络连接 远程存储系统通过计算机的网络接口使用管理处理器,通过网络连接将原始图像通过分布式文件系统协议发送到远程存储系统。

    Software-based power capping
    25.
    发明授权
    Software-based power capping 有权
    基于软件的电源封顶

    公开(公告)号:US08464086B2

    公开(公告)日:2013-06-11

    申请号:US12920575

    申请日:2008-03-03

    申请人: Darren J. Cepulis

    发明人: Darren J. Cepulis

    IPC分类号: G06F1/32

    摘要: The present invention relates to power consumption, and specifically an apparatus, method, and computer readable medium to manage and control power consumption in computer systems. Specifically, the present invention manages power consumption by controlling the types of threads that are executed by the processor. The present invention monitors the resources of the system to determine the power consumption of the system. If the power consumption is too high, the present invention issues more low power threads to be executed by the processor.

    摘要翻译: 本发明涉及功耗,特别涉及一种用于管理和控制计算机系统功耗的装置,方法和计算机可读介质。 具体地,本发明通过控制由处理器执行的线程的类型来管理功耗。 本发明监控系统的资源以确定系统的功耗。 如果功耗太高,则本发明发出更多的低功率线程来执行处理器。

    Method for expansion and integration of option ROM support utilities for run-time/boot-time usage
    26.
    发明授权
    Method for expansion and integration of option ROM support utilities for run-time/boot-time usage 失效
    扩展和集成选项ROM支持实用程序的方法,用于运行时/引导时使用

    公开(公告)号:US06961791B2

    公开(公告)日:2005-11-01

    申请号:US09981202

    申请日:2001-10-17

    申请人: Darren J. Cepulis

    发明人: Darren J. Cepulis

    IPC分类号: G06F9/445 G06F13/00

    CPC分类号: G06F9/4411

    摘要: A computer system has a centralized configuration control point. Preferably, this control point is a ROM-based setup utility (“RBSU”) which permits various aspects of the computer system to configured such as system passwords, serial ports, parallel ports, and the like. The RBSU also permits an operator to configure various option device and subsystems, such as PCI devices. When such an option device is selected to be configured, the RBSU code searches option ROM space for one or more predefined signature values. Such a signature, which preferably comprises an eight byte value, signifies the beginning of a table of information which the RBSU code uses to determine the location of the beginning of the option ROM routine through which the corresponding option device can be configured. Once the option device is configured, control returns to the RBSU code. In this way, the operator can configure the computer system and the option devices from a single software control system.

    摘要翻译: 计算机系统具有集中式配置控制点。 优选地,该控制点是基于ROM的设置实用程序(“RBSU”),其允许计算机系统的各个方面被配置为诸如系统密码,串行端口,并行端口等。 RBSU还允许操作员配置各种选项设备和子系统,如PCI设备。 当选择这样的选项设备来配置时,RBSU代码搜索用于一个或多个预定义签名值的选项ROM空间。 优选地包括八字节值的签名表示RBSU代码用于确定可以配置相应的选项设备的选项ROM例程的开始位置的信息表的开始。 一旦配置了选件设备,控制返回到RBSU代码。 以这种方式,操作员可以从单个软件控制系统配置计算机系统和选项设备。

    Computer system implementing fault detection and isolation using unique identification codes stored in non-volatile memory
    27.
    发明授权
    Computer system implementing fault detection and isolation using unique identification codes stored in non-volatile memory 有权
    计算机系统使用存储在非易失性存储器中的唯一识别码实现故障检测和隔离

    公开(公告)号:US06463550B1

    公开(公告)日:2002-10-08

    申请号:US09267587

    申请日:1999-03-12

    IPC分类号: G06F1134

    摘要: A computer system implementing a fault detection and isolation technique tracks failed physical devices by error codes embedded in various component in the computer system. The computer system comprises one or more CPU's, one or more memory modules, a master control device, such as an I2C master, and a North bridge logic device coupling together the CPU's, memory modules, and master control device. The master control device also connects to the CPU's and memory modules over a serial bus, such as an I2C bus. Each component includes a nonvolatile memory coupled to the I2C bus for storing error information. If a component fails, a CPU stores an error code into the nonvolatile memory via the I2C bus. During initialization, the CPU creates a logical resource map which includes a list of logical addresses of all available (i.e., fully functional) devices. The logical resource map is provided to the computer's operating system which isolates failed devices by only permitting access to those logical devices listed as available. The computer may include a non-volatile memory device coupled to the CPU for storing a failed device log which includes a list of ID codes corresponding to failed physical devices. After a device is determined to be non-functional, one of the CPU's stores that device's unique ID code in the failed device log. During system initialization, the information in the failed device log is compared to the error information stored in the components to create the logical resource map.

    摘要翻译: 实施故障检测和隔离技术的计算机系统通过计算机系统中嵌入在各种组件中的错误代码跟踪故障物理设备。 计算机系统包括一个或多个CPU,一个或多个存储器模块,诸如I2C主机的主控制装置以及将CPU,存储器模块和主控制装置耦合在一起的北桥逻辑装置。 主控制器还通过串行总线(如I2C总线)连接到CPU和内存模块。 每个组件包括耦合到I2C总线的非易失性存储器,用于存储错误信息。 如果组件发生故障,CPU将错误代码通过I2C总线存储到非易失性存储器中。 在初始化期间,CPU创建逻辑资源映射,其包括所有可用(即完全功能的)设备的逻辑地址的列表。 逻辑资源映射被提供给计算机的操作系统,其通过仅允许访问列出的可用的逻辑设备来隔离故障设备。 计算机可以包括耦合到CPU的非易失性存储器设备,用于存储故障设备日志,其包括与故障物理设备相对应的ID代码的列表。 在设备被确定为非功能之后,其中一个CPU将设备的唯一ID代码存储在故障设备日志中。 在系统初始化期间,将故障设备日志中的信息与存储在组件中的错误信息进行比较,以创建逻辑资源映射。

    Resetting multiple processors in a computer system
    28.
    发明授权
    Resetting multiple processors in a computer system 失效
    在计算机系统中重置多个处理器

    公开(公告)号:US06314515B1

    公开(公告)日:2001-11-06

    申请号:US09356472

    申请日:1999-07-19

    IPC分类号: G06F15177

    摘要: Two design variations which allow multiple processors to start up using a single ROM are disclosed. In each design, a single, primary processor is allowed to perform a complete POST while the remaining, secondary processors are directed in the course of their POST to perform a more limited initialization sequence. At power on, the primary processor begins a normal POST, while the secondary processors are held until a vector is placed into a redirection vector location. Each secondary processor is then subsequently started, using its own initialization code located at the address indicated by the redirection vector. The first technique is applicable to general multiprocessor systems because the implementation of this design can be run either from external software or from an addition to the operating system of the particular machine on which it is being used. The second technique is more specifically oriented to a particular system, and includes the use of an identity register to differentiate between primary and secondary processors.

    摘要翻译: 公开了允许使用单个ROM启动多个处理器的两种设计变型。 在每个设计中,允许单个主处理器执行完整的POST,而剩余的辅助处理器在其POST过程中被引导以执行更有限的初始化序列。 上电时,主处理器开始正常POST,而辅助处理器保持,直到向量放置到重定向向量位置。 然后,使用其位于由重定向向量指示的地址处的自己的初始化代码随后启动每个二级处理器。 第一种技术适用于一般的多处理器系统,因为这种设计的实现可以从外部软件运行,也可以从添加到正在使用它的特定机器的操作系统运行。 第二种技术更具体地针对特定系统,并且包括使用身份寄存器来区分主处理器和辅助处理器。

    Method and apparatus for resetting multiple processors using a common ROM
    29.
    发明授权
    Method and apparatus for resetting multiple processors using a common ROM 失效
    使用公共ROM复位多个处理器的方法和装置

    公开(公告)号:US5497497A

    公开(公告)日:1996-03-05

    申请号:US51601

    申请日:1993-04-22

    摘要: Two design variations which allow multiple processors to start up using a single ROM. In each design, a single, primary processor is allowed to perform a complete POST while the remaining, secondary processors are directed in the course of their POST to perform a more limited initialization sequence. At power on, the primary processor begins a normal POST, while the secondary processors are held until a vector is placed into a redirection vector location. Each secondary processor is then subsequently started, using its own initialization code located at the address indicated by the redirection vector. The first technique is applicable to general multiprocessor systems because the implementation of this design can be run either from external software or from an addition to the operating system of the particular machine on which it is being used. The second technique is more specifically oriented to a particular system, and includes the use of an identity register to differentiate between primary and secondary processors.

    摘要翻译: 两种设计变化,允许多个处理器使用单个ROM启动。 在每个设计中,允许单个主处理器执行完整的POST,而剩余的辅助处理器在其POST过程中被引导以执行更有限的初始化序列。 上电时,主处理器开始正常POST,而辅助处理器保持,直到向量放置到重定向向量位置。 然后,使用其位于由重定向向量指示的地址处的自己的初始化代码随后启动每个二级处理器。 第一种技术适用于一般的多处理器系统,因为这种设计的实现可以从外部软件运行,也可以从添加到正在使用它的特定机器的操作系统运行。 第二种技术更具体地针对特定系统,并且包括使用身份寄存器来区分主处理器和辅助处理器。