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33 条记录 (耗时 0.043 秒)

    High performance CMOS device structure with mid-gap metal gate
    21.
    发明授权
    High performance CMOS device structure with mid-gap metal gate 失效
    高性能CMOS器件结构，具有中间间隙金属栅极

    公开(公告)号：US06916698B2

    公开(公告)日：2005-07-12

    申请号：US10795672

    申请日：2004-03-08

    申请人： Anda C. Mocuta ,  Meikei Ieong ,  Ricky S. Amos ,  Diane C. Boyd ,  Dan M. Mocuta ,  Huajie Chen

    发明人： Anda C. Mocuta ,  Meikei Ieong ,  Ricky S. Amos ,  Diane C. Boyd ,  Dan M. Mocuta ,  Huajie Chen

    IPC分类号： H01L29/423 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/49

    CPC分类号： H01L21/823807 ,  H01L21/823828

    摘要： High performance (surface channel) CMOS devices with a mid-gap work function metal gate are disclosed wherein an epitaxial layer is used for a threshold voltage Vt adjust/decrease for the PFET area, for large Vt reductions (˜500 mV), as are required by CMOS devices with a mid-gap metal gate. The present invention provides counter doping using an in situ B doped epitaxial layer or a B and C co-doped epitaxial layer, wherein the C co-doping provides an additional degree of freedom to reduce the diffusion of B (also during subsequent activation thermal cycles) to maintain a shallow B profile, which is critical to provide a surface channel CMOS device with a mid-gap metal gate while maintaining good short channel effects. The B diffusion profiles are satisfactorily shallow, sharp and have a high B concentration for devices with mid-gap metal gates, to provide and maintain a thin, highly doped B layer under the gate oxide.

    摘要翻译： 公开了具有中间间隙功函数金属栅极的高性能（表面沟道）CMOS器件，其中外延层用于PFET区域的阈值电压Vt调整/减小，用于大的Vt降低（〜500mV），如 需要具有中间间隙金属栅极的CMOS器件。 本发明提供了使用原位B掺杂外延层或B和C共掺杂外延层的反掺杂，其中C共掺杂提供了额外的自由度以减少B的扩散（也在随后的激活热循环期间） ）以保持浅的B剖面，这对于提供具有中间间隙金属栅极的表面沟道CMOS器件而言是至关重要的，同时保持良好的短沟道效应。 对于具有中间间隙金属栅极的器件，B扩散曲线令人满意地浅，尖锐且具有高B浓度，以在栅极氧化物下提供并保持薄的高掺杂B层。

    Method of forming a fully-depleted SOI ( silicon-on-insulator) MOSFET having a thinned channel region
    22.
    发明授权
    Method of forming a fully-depleted SOI ( silicon-on-insulator) MOSFET having a thinned channel region 失效
    形成具有稀疏沟道区的完全耗尽的SOI（绝缘体上硅）MOSFET的方法

    公开(公告)号：US06660598B2

    公开(公告)日：2003-12-09

    申请号：US10084550

    申请日：2002-02-26

    申请人： Hussein I. Hanafi ,  Diane C. Boyd ,  Kevin K. Chan ,  Wesley Natzle ,  Leathen Shi

    发明人： Hussein I. Hanafi ,  Diane C. Boyd ,  Kevin K. Chan ,  Wesley Natzle ,  Leathen Shi

    IPC分类号： H01L21336

    CPC分类号： H01L29/78696 ,  H01L29/66545 ,  H01L29/66772 ,  H01L29/78612

    摘要： A sub-0.05 &mgr;m channel length fully-depleted SOI MOSFET device having low source and drain resistance and minimal overlap capacitance and a method of fabricating the same are provided. In accordance with the method of the present invention, at least one dummy gate region is first formed atop an SOI layer. The dummy gate region includes at least a sacrificial polysilicon region and first nitride spacers located on sidewalls of the sacrificial polysilicon region. Next, an oxide layer that is coplanar with an upper surface of the dummy gate region is formed and then the sacrificial polysilicon region is removed to expose a portion of the SOI layer. A thinned device channel region is formed in the exposed portion of the SOI layer and thereafter inner nitride spacers are formed on exposed walls of the fist nitride spacers. Next, a gate region is formed over the thinned device channel region and then the oxide layer is removed so as to expose thicker portions of the SOI layer than de device channel region.

    摘要翻译： 提供了具有低源极和漏极电阻以及最小重叠电容的0.05微米通道长度的全耗尽SOI MOSFET器件及其制造方法。 根据本发明的方法，首先在SOI层顶部形成至少一个虚拟栅极区域。 虚拟栅极区域至少包括牺牲多晶硅区域和位于牺牲多晶硅区域的侧壁上的第一氮化物间隔物。 接下来，形成与伪栅极区的上表面共面的氧化物层，然后除去牺牲多晶硅区域，以露出SOI层的一部分。 在SOI层的暴露部分中形成一个变薄的器件沟道区，此后在第一氮化物间隔物的暴露的壁上形成内部氮化物间隔物。 接下来，在减薄的器件沟道区上形成栅极区，然后除去氧化物层，以便暴露出SOI层的比较器件沟道区更厚的部分。

    Hybrid planar and FinFET CMOS devices
    27.
    发明授权
    Hybrid planar and FinFET CMOS devices 有权
    混合平面和FinFET CMOS器件

    公开(公告)号：US07250658B2

    公开(公告)日：2007-07-31

    申请号：US11122193

    申请日：2005-05-04

    申请人： Bruce B. Doris ,  Diane C. Boyd ,  Meikei Leong ,  Thomas S. Kanarsky ,  Jakub T. Kedzierski ,  Min Yang

    发明人： Bruce B. Doris ,  Diane C. Boyd ,  Meikei Leong ,  Thomas S. Kanarsky ,  Jakub T. Kedzierski ,  Min Yang

    IPC分类号： H01L29/772

    CPC分类号： H01L27/1211 ,  H01L21/845 ,  H01L29/66795 ,  H01L29/785

    摘要： The present invention provides an integrated semiconductor circuit containing a planar single gated FET and a FinFET located on the same SOI substrate. Specifically, the integrated semiconductor circuit includes a FinFET and a planar single gated FET located atop a buried insulating layer of an silicon-on-insulator substrate, the planar single gated FET is located on a surface of a patterned top semiconductor layer of the silicon-on-insulator substrate and the FinFET has a vertical channel that is perpendicular to the planar single gated FET. A method of forming a method such an integrated circuit is also provided. In the method, resist imaging and a patterned hard mask are used in trimming the width of the FinFET active device region and subsequent resist imaging and etching are used in thinning the thickness of the FET device area. The trimmed active FinFET device region is formed such that it lies perpendicular to the thinned planar single gated FET device region.

    摘要翻译： 本发明提供一种集成半导体电路，其包含位于同一SOI衬底上的平面单栅极FET和FinFET。 具体地，集成半导体电路包括FinFET和位于绝缘体上硅衬底的掩埋绝缘层顶上的平面单栅极FET，平面单门控FET位于硅 - 硅绝缘体的图案化顶部半导体层的表面上， 绝缘体上的衬底和FinFET具有垂直于平面单门控FET的垂直沟道。 还提供了一种形成集成电路的方法。 在该方法中，抗蚀剂成像和图案化的硬掩模用于修整FinFET有源器件区域的宽度，并且随后的抗蚀剂成像和蚀刻用于减薄FET器件区域的厚度。 经修整的有源FinFET器件区域形成为垂直于薄化的平面单栅极FET器件区域。

    CMOS transistor structure including film having reduced stress by exposure to atomic oxygen
    28.
    发明授权
    CMOS transistor structure including film having reduced stress by exposure to atomic oxygen 失效
    CMOS晶体管结构包括通过暴露于原子氧而具有减小的应力的膜

    公开(公告)号：US07202516B2

    公开(公告)日：2007-04-10

    申请号：US11318844

    申请日：2005-12-27

    申请人： Michael P. Belyansky ,  Diane C. Boyd ,  Bruce B. Doris ,  Oleg Gluschenkov

    发明人： Michael P. Belyansky ,  Diane C. Boyd ,  Bruce B. Doris ,  Oleg Gluschenkov

    IPC分类号： H01L29/80

    CPC分类号： H01L29/7843 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/84 ,  H01L27/1203

    摘要： A structure and method are provided in which a stress present in a film is reduced in magnitude by oxidizing the film through atomic oxygen supplied to a surface of the film. In an embodiment, a mask is used to selectively block portions of the film so that the stress is relaxed only in areas exposed to the oxidation process. A structure and method are further provided in which a film having a stress is formed over source and drain regions of an NFET and a PFET. The stress present in the film over the source and drain regions of either the NFET or the PFET is then relaxed by oxidizing the film through exposure to atomic oxygen to provide enhanced mobility in at least one of the NFET or the PFET while maintaining desirable mobility in the other of the NFET and PFET.

    摘要翻译： 提供了一种结构和方法，其中通过供应到膜的表面的原子氧氧化膜来减小膜中存在的应力。 在一个实施例中，掩模用于选择性地阻挡膜的部分，使得应力仅在暴露于氧化过程的区域中松弛。 还提供了一种结构和方法，其中在NFET和PFET的源极和漏极区域上形成具有应力的膜。 然后在NFET或PFET的源极和漏极区域上存在于膜中的应力通过暴露于原子氧氧化膜而被松弛，以在至少一个NFET或PFET中提供增强的迁移率，同时保持理想的迁移率 另一个是NFET和PFET。

    SOI wafers with 30-100 Å buried oxide (BOX) created by wafer bonding using 30-100 Å thin oxide as bonding layer
    29.
    发明授权
    SOI wafers with 30-100 Å buried oxide (BOX) created by wafer bonding using 30-100 Å thin oxide as bonding layer 有权
    具有30-100埃埋层氧化物（BOX）的SOI晶片通过使用30-100薄氧化物作为结合层的晶片接合而产生

    公开(公告)号：US07166521B2

    公开(公告)日：2007-01-23

    申请号：US10957833

    申请日：2004-10-04

    申请人： Diane C. Boyd ,  Hussein I. Hanafi ,  Erin C. Jones ,  Dominic J. Schepis ,  Leathen Shi

    发明人： Diane C. Boyd ,  Hussein I. Hanafi ,  Erin C. Jones ,  Dominic J. Schepis ,  Leathen Shi

    IPC分类号： H01L21/30 ,  H01L21/46 ,  H01L21/21 ,  H01L21/36 ,  H01L21/425

    CPC分类号： H01L21/76251 ,  H01L21/76243

    摘要： A method of fabricating a SOI wafer having a gate-quality, thin buried oxide region is provided. The wafer is fabricating by forming a substantially uniform thermal oxide on a surface of a Si-containing layer of a SOI substrate which includes a buried oxide region positioned between the Si-containing layer and a Si-containing substrate layer. Next, a cleaning process is employed to form a hydrophilic surface on the thermal oxide. A carrier wafer having a hydrophilic surface is provided and positioned near the substrate such that the hydrophilic surfaces adjoin each other. Room temperature bonding is then employed to bond the carrier wafer to the substrate. An annealing step is performed and thereafter, the Si-containing substrate of the silicon-on-insulator substrate and the buried oxide region are selectively removed to expose the Si-containing layer.

    摘要翻译： 提供一种制造具有栅极质量薄的掩埋氧化物区域的SOI晶片的方法。 通过在SOI衬底的含Si层的表面上形成基本上均匀的热氧化物来制造晶片，该衬底包括位于含Si层和含Si衬底层之间的掩埋氧化物区域。 接下来，使用清洁方法在热氧化物上形成亲水性表面。 提供具有亲水表面的载体晶片并且将其定位在基板附近，使得亲水表面彼此相邻。 然后使用室温粘合将载体晶片粘合到基底上。 进行退火工序，然后选择性地除去绝缘体上硅衬底的含硅衬底和掩埋氧化物区域以暴露含Si层。