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8 条记录 (耗时 0.031 秒)

    Hybrid planar and FinFET CMOS devices
    1.
    发明授权
    Hybrid planar and FinFET CMOS devices 有权
    混合平面和FinFET CMOS器件

    公开(公告)号：US07250658B2

    公开(公告)日：2007-07-31

    申请号：US11122193

    申请日：2005-05-04

    申请人： Bruce B. Doris ,  Diane C. Boyd ,  Meikei Leong ,  Thomas S. Kanarsky ,  Jakub T. Kedzierski ,  Min Yang

    发明人： Bruce B. Doris ,  Diane C. Boyd ,  Meikei Leong ,  Thomas S. Kanarsky ,  Jakub T. Kedzierski ,  Min Yang

    IPC分类号： H01L29/772

    CPC分类号： H01L27/1211 ,  H01L21/845 ,  H01L29/66795 ,  H01L29/785

    摘要： The present invention provides an integrated semiconductor circuit containing a planar single gated FET and a FinFET located on the same SOI substrate. Specifically, the integrated semiconductor circuit includes a FinFET and a planar single gated FET located atop a buried insulating layer of an silicon-on-insulator substrate, the planar single gated FET is located on a surface of a patterned top semiconductor layer of the silicon-on-insulator substrate and the FinFET has a vertical channel that is perpendicular to the planar single gated FET. A method of forming a method such an integrated circuit is also provided. In the method, resist imaging and a patterned hard mask are used in trimming the width of the FinFET active device region and subsequent resist imaging and etching are used in thinning the thickness of the FET device area. The trimmed active FinFET device region is formed such that it lies perpendicular to the thinned planar single gated FET device region.

    摘要翻译： 本发明提供一种集成半导体电路，其包含位于同一SOI衬底上的平面单栅极FET和FinFET。 具体地，集成半导体电路包括FinFET和位于绝缘体上硅衬底的掩埋绝缘层顶上的平面单栅极FET，平面单门控FET位于硅 - 硅绝缘体的图案化顶部半导体层的表面上， 绝缘体上的衬底和FinFET具有垂直于平面单门控FET的垂直沟道。 还提供了一种形成集成电路的方法。 在该方法中，抗蚀剂成像和图案化的硬掩模用于修整FinFET有源器件区域的宽度，并且随后的抗蚀剂成像和蚀刻用于减薄FET器件区域的厚度。 经修整的有源FinFET器件区域形成为垂直于薄化的平面单栅极FET器件区域。

    Hybrid planar and finFET CMOS devices
    2.
    发明授权
    Hybrid planar and finFET CMOS devices 失效
    混合平面和finFET CMOS器件

    公开(公告)号：US06911383B2

    公开(公告)日：2005-06-28

    申请号：US10604097

    申请日：2003-06-26

    申请人： Bruce B. Doris ,  Diane C. Boyd ,  Meikei Ieong ,  Thomas S. Kanarsky ,  Jakub T. Kedzierski ,  Min Yang

    发明人： Bruce B. Doris ,  Diane C. Boyd ,  Meikei Ieong ,  Thomas S. Kanarsky ,  Jakub T. Kedzierski ,  Min Yang

    IPC分类号： H01L29/423 ,  H01L21/336 ,  H01L21/8234 ,  H01L21/84 ,  H01L27/08 ,  H01L27/088 ,  H01L27/12 ,  H01L29/49 ,  H01L29/786 ,  H01L21/3205

    CPC分类号： H01L27/1211 ,  H01L21/845 ,  H01L29/66795 ,  H01L29/785

    摘要： The present invention provides an integrated semiconductor circuit containing a planar single gated FET and a FinFET located on the same SOI substrate. Specifically, the integrated semiconductor circuit includes a FinFET and a planar single gated FET located atop a buried insulating layer of an silicon-on-insulator substrate, the planar single gated FET is located on a surface of a patterned top semiconductor layer of the silicon-on-insulator substrate and the FinFET has a vertical channel that is perpendicular to the planar single gated FET. A method of forming a method such an integrated circuit is also provided. In the method, resist imaging and a patterned hard mask are used in trimming the width of the FinFET active device region and subsequent resist imaging and etching are used in thinning the thickness of the FET device area. The trimmed active FinFET device region is formed such that it lies perpendicular to the thinned planar single gated FET device region.

    摘要翻译： 本发明提供一种集成半导体电路，其包含位于同一SOI衬底上的平面单栅极FET和FinFET。 具体地，集成半导体电路包括FinFET和位于绝缘体上硅衬底的掩埋绝缘层顶上的平面单栅极FET，平面单门控FET位于硅 - 硅绝缘体的图案化顶部半导体层的表面上， 绝缘体上的衬底和FinFET具有垂直于平面单门控FET的垂直沟道。 还提供了一种形成集成电路的方法。 在该方法中，抗蚀剂成像和图案化的硬掩模用于修整FinFET有源器件区域的宽度，并且随后的抗蚀剂成像和蚀刻用于减薄FET器件区域的厚度。 经修整的有源FinFET器件区域形成为垂直于薄化的平面单栅极FET器件区域。

    Method and apparatus for fabricating CMOS field effect transistors
    8.
    发明授权
    Method and apparatus for fabricating CMOS field effect transistors 失效
    制造CMOS场效应晶体管的方法和装置

    公开(公告)号：US07183182B2

    公开(公告)日：2007-02-27

    申请号：US10669898

    申请日：2003-09-24

    申请人： Cyril Cabral, Jr. ,  Meikei Ieong ,  Jakub T. Kedzierski

    发明人： Cyril Cabral, Jr. ,  Meikei Ieong ,  Jakub T. Kedzierski

    IPC分类号： H01L21/425

    CPC分类号： H01L29/66628 ,  H01L21/28052 ,  H01L21/28097 ,  H01L21/823835

    摘要： A method of fabricating complementary metal oxide semiconductor (CMOS) field effect transistors which includes selective doping and full silicidation of a polysilicon material comprising the gate electrode of the transistor. In one embodiment, prior to silicidation, the polysilicon is amorphized. In a further embodiment, siliciding is performed at a low substrate temperature.

    摘要翻译： 制造互补金属氧化物半导体（CMOS）场效应晶体管的方法，其包括选择性掺杂和包括晶体管的栅电极的多晶硅材料的全硅化。 在一个实施方案中，在硅化之前，多晶硅是非晶化的。 在另一个实施方案中，在低的衬底温度下进行硅化。