公开(公告)号：US06919255B2

公开(公告)日：2005-07-19

申请号：US10630373

申请日：2003-07-30

Applicant: Albert Birner ,  Matthias Goldbach ,  Thomas Hecht ,  Lars Heineck ,  Stephan Kudelka ,  Jörn Lützen ,  Dirk Manger ,  Andreas Orth

Inventor： Albert Birner ,  Matthias Goldbach ,  Thomas Hecht ,  Lars Heineck ,  Stephan Kudelka ,  Jörn Lützen ,  Dirk Manger ,  Andreas Orth

IPC: H01L27/108 ,  H01L21/00 ,  H01L21/20 ,  H01L21/334 ,  H01L21/8242 ,  H01L29/94

CPC classification number: H01L27/1087 ,  H01L29/66181 ,  H01L29/945

Abstract: A method for fabricating a semiconductor trench structure includes forming a trench in a semiconductor substrate and filling it with a filler. A first thermal process having a first maximum temperature cures the filler. Removing the filler from an upper region of the trench as far as a boundary surface defines a collar region. In a second thermal process having a second maximum temperature that is not significantly higher than the first maximum temperature, a liner is deposited on the collar region and the boundary surface. The liner is removed from the boundary surface, thereby exposing the filler. The filler is then removed from a lower region of the trench.

Abstract translation: 一种制造半导体沟槽结构的方法包括在半导体衬底中形成沟槽并用填充物填充沟槽。 具有第一最高温度的第一热处理固化填料。 从沟槽的上部区域移除填料至达边界表面限定了一个环形区域。 在具有不显着高于第一最高温度的第二最高温度的第二热处理中，衬套沉积在套环区域和边界表面上。 将衬垫从边界表面移除，从而暴露填料。 然后从沟槽的下部区域去除填料。

公开(公告)号：US20050032309A1

公开(公告)日：2005-02-10

申请号：US10850960

申请日：2004-05-21

Applicant: Dirk Manger

Inventor： Dirk Manger

IPC: H01L21/8242 ,  H01L27/108 ,  H01L21/336

CPC classification number: H01L27/10864 ,  H01L27/10841 ,  H01L27/1087

Abstract: A memory cell has a vertical construction of a capacitor and a vertical FET arranged above the latter which can be produced with a lower outlay and in a technologically more reliable fashion. This is achieved by virtue of the fact that two first trenches running parallel and having a first depth are etched in the semiconductor substrate. Between the trenches is formed a web, which is connected to the semiconductor substrate at its narrow sides and which is severed at its underside and is separated from the semiconductor substrate. The suspended web is then provided with a closed dielectric. After a filling, the FET is applied and connected to the web as memory node.

Abstract translation: 存储单元具有垂直构造的电容器和布置在其上方的垂直FET，其可以以较低的开销和技术上更可靠的方式产生。 这是通过在半导体衬底中蚀刻平行且具有第一深度的两个第一沟槽来实现的。 在沟槽之间形成网状物，该网状物在其窄边连接到半导体衬底，并且在其下侧被切断并与半导体衬底分离。 然后，悬挂的网带有封闭的电介质。 填充后，施加FET并将其连接到作为存储器节点的网。

公开(公告)号：US20090309152A1

公开(公告)日：2009-12-17

申请号：US12137388

申请日：2008-06-11

Applicant: Roman Knoefler ,  Michael Specht ,  Franz Hofmann ,  Florian Beug ,  Dirk Manger ,  Stephan Riedel

Inventor： Roman Knoefler ,  Michael Specht ,  Franz Hofmann ,  Florian Beug ,  Dirk Manger ,  Stephan Riedel

IPC: H01L29/792 ,  H01L21/336

CPC classification number: H01L21/28282 ,  H01L21/28273 ,  H01L21/8221 ,  H01L27/11565 ,  H01L27/11568 ,  H01L27/11578 ,  H01L27/11582 ,  H01L29/792 ,  H01L29/7926

Abstract: In an embodiment, an integrated circuit having a memory cell arrangement is provided. The memory cell arrangement may include a substrate, a fin structure disposed above the substrate, and a memory cell contacting region. The fin structure may include a memory cell region having a plurality of memory cell structures being disposed above one another, each memory cell structure having an active region of a respective memory cell. Furthermore, the memory cell contacting region may be configured to electrically contact each of the memory cell structures, wherein the memory cell contacting region may include a plurality of contact regions, which are at least partially displaced with respect to each other in a direction parallel to the main processing surface of the substrate.

Abstract translation: 在一个实施例中，提供了具有存储单元布置的集成电路。 存储单元布置可以包括基板，设置在基板上方的散热片结构和存储单元接触区域。 鳍结构可以包括具有多个存储单元结构的存储单元区域，每个存储单元结构具有相应存储单元的有源区域。 此外，存储器单元接触区域可以被配置为电接触每个存储单元结构，其中存储单元接触区域可以包括多个接触区域，这些接触区域在平行于存储器单元结构的方向上相对于彼此至少部分地位移 基材的主要加工表面。

公开(公告)号：US07339224B2

公开(公告)日：2008-03-04

申请号：US10482154

申请日：2002-06-12

Applicant: Dirk Manger

Inventor： Dirk Manger

IPC: H01L29/94

CPC classification number: H01L27/10861 ,  H01L27/10829 ,  H01L27/10867 ,  H01L29/66181

Abstract: The invention relates to a trench capacitor, in particular for use in a semiconductor memory cell, comprising a trench (2), embodied in a substrate (1), a first region (1a), provided in the substrate (1), as first capacitor electrode, a dielectric layer (10) on the trench wall as capacitor dielectric and a metallic filler material (30″) provided in the trench (2) as second electrode. Above the conducting metallic filling material (30″) a dielectric filling material (35) is provided in the trench (2) with a cavity (40) provided for mechanical tensions. The invention further relates to a corresponding method of production.

Abstract translation: 本发明涉及一种沟槽电容器，特别是用于半导体存储器单元中的沟槽电容器，其包括在衬底（1）中实施的沟槽（2），设置在衬底（1）中的第一区域（1a），如 第一电容器电极，作为电容器电介质的沟槽壁上的介电层（10）和作为第二电极设置在沟槽（2）中的金属填充材料（30“）。 在导电金属填充材料（30“）上方，介电填充材料（35）在沟槽（2）中设置有用于机械张力的空腔（40）。 本发明还涉及相应的生产方法。

公开(公告)号：US20070254442A1

公开(公告)日：2007-11-01

申请号：US11414553

申请日：2006-05-01

Applicant: Dirk Manger ,  Jyoti Gupta ,  Christoph Ludwig ,  Hans Lindemann

Inventor： Dirk Manger ,  Jyoti Gupta ,  Christoph Ludwig ,  Hans Lindemann

IPC: H01L21/336

CPC classification number: H01L21/28247 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833

Abstract: A growth material that grows selectively on the vertical sidewalls of a vertical device forms sidewall spacers on substantially vertical sidewalls of the vertical device that is disposed on a horizontal substrate surface of a semiconductor substrate. A spacer-like seed liner may be provided on the vertical sidewalls of the vertical device to control selective growth. The vertical device may be a gate electrode of a field effect transistor (FET). With selectively grown sidewall spacers, heavily doped contact regions of the FET may be precisely spaced apart from the gate electrode. The distance of the heavily doped contact regions to the gate electrode does not depend from the height of the gate electrode. Distances of more than 150 nm between the heavily doped contact region and the gate electrode may be achieved so as to facilitate the formation of, for example, DMOS devices.

Abstract translation: 选择性地在垂直装置的垂直侧壁上生长的生长材料在垂直装置的基本上垂直的侧壁上形成侧壁间隔物，其设置在半导体衬底的水平衬底表面上。 可以在垂直装置的垂直侧壁上设置间隔物种子衬垫，以控制选择性生长。 垂直装置可以是场效应晶体管（FET）的栅电极。 利用选择性地生长的侧壁间隔物，FET的重掺杂接触区域可以与栅电极精确地间隔开。 重掺杂的接触区域与栅电极的距离不取决于栅电极的高度。 可以实现重掺杂接触区域和栅电极之间超过150nm的距离，以便于例如DMOS器件的形成。

公开(公告)号：US20070037345A1

公开(公告)日：2007-02-15

申请号：US11203404

申请日：2005-08-15

Applicant: Dirk Manger

Inventor： Dirk Manger

IPC: H01L21/8242

CPC classification number: H01L27/10855 ,  H01L27/10817 ,  H01L28/91

Abstract: A method of forming a memory cell array including a plurality of memory cells includes patterning isolation trenches on a semiconductor substrate and filling with an insulating material to define active area lines. In particular, the isolation trenches are patterned as straight lines, resulting in the active area lines being formed as straight lines. After forming word lines incorporating a plurality of gate electrodes, isolation grooves are formed by etching the semiconductor substrate material using the gate electrodes as an etching mask. The active area segments are isolated from each other by a self-aligned etching step. Thereafter, the transistors are completed by defining the first and second source/drain regions, and the remaining parts of the memory cells, in particular, the capacitor contacts, the bit lines and the storage capacitors are formed.

Abstract translation: 形成包括多个存储单元的存储单元阵列的方法包括：图案化半导体衬底上的隔离沟槽并填充绝缘材料以限定有源面积线。 特别地，隔离沟槽被图案化为直线，导致有源面积线形成为直线。 在形成包含多个栅电极的字线之后，通过使用栅电极作为蚀刻掩模蚀刻半导体衬底材料来形成隔离沟槽。 有源区段通过自对准蚀刻步骤彼此隔离。 此后，通过限定第一和第二源/漏区来完成晶体管，并且形成存储单元的其余部分，特别是电容器触点，位线和存储电容器。

公开(公告)号：US07109544B2

公开(公告)日：2006-09-19

申请号：US10777128

申请日：2004-02-13

Applicant: Till Schloesser ,  Dirk Manger ,  Bernd Goebel

Inventor： Till Schloesser ,  Dirk Manger ,  Bernd Goebel

IPC: H01L27/108

CPC classification number: H01L27/10876 ,  H01L27/10823

Abstract: In a substrate vertical transistor cells are formed and are arranged, in a transistor cell array, row by row in an x direction and column by column in a y direction. Lower source/drain regions of the transistor cells are connected to a common connection plate. Upper source/drain regions of the transistor cells impart a contact connection for instance to a storage capacitor of a DRAM memory cell. Active trenches running between the transistor cells with word lines are formed along the x direction. The word lines form gate electrodes in sections. A potential at the gate electrode controls a conductive channel in an active region arranged in each case between the upper and the lower source/drain connection region. According to the invention, the active regions of adjacent transistor cells are sections of a contiguous layer body and are connected to one another. An accumulation of charge carriers in the active region and floating body effects are avoided without increasing the area requirement of a transistor cell.

Abstract translation: 在衬底中，垂直晶体管单元被形成并且在晶体管单元阵列中沿x方向逐行排列并且沿y方向逐列地排列。 晶体管单元的较低源极/漏极区域连接到公共连接板。 晶体管单元的上部源极/漏极区域例如向DRAM存储单元的存储电容器提供接触连接。 沿着x方向形成在具有字线的晶体管单元之间运行的有源沟槽。 字线形成栅电极。 在栅电极处的电位控制在每个情况下布置在上下源极/漏极连接区域之间的有源区中的导电沟道。 根据本发明，相邻晶体管单元的有源区是连续层体的部分并彼此连接。 在不增加晶体管单元的面积要求的情况下避免了有源区中的电荷载流子的积累和浮体效应。

公开(公告)号：US20050083724A1

公开(公告)日：2005-04-21

申请号：US10898706

申请日：2004-07-23

Applicant: Dirk Manger ,  Till Schloesser ,  Rolf Weis ,  Bernd Goebel ,  Wolfgang Mueller

Inventor： Dirk Manger ,  Till Schloesser ,  Rolf Weis ,  Bernd Goebel ,  Wolfgang Mueller

IPC: G11C11/34 ,  H01L21/8242 ,  H01L27/108

CPC classification number: H01L27/10867 ,  H01L27/10841 ,  H01L27/10876 ,  H01L27/10888 ,  H01L27/10891

Abstract: Memory cells each having a cell capacitor and a cell transistor, which are arranged in a vertical cell structure, are provided in the cell array of a DRAM. By means of a deep implantation or a shallow implantation and subsequent epitaxial growth of silicon, a buried source/drain layer is formed, from which lower source/drain regions of the cell transistors emerge. The upper edge of the buried source/drain layer can be aligned with respect to a lower edge of a gate electrode of the cell transistor and this results in a reduction of a gate/drain capacitance and also a leakage current between the gate electrode and the lower source/drain region. A body connection plate for the connection of the channel regions is applied to the substrate surface and contact holes are introduced into the body connection plate. Upper source/drain regions of the cell transistors are formed by implantation through the contact holes.

Abstract translation: 每个具有单元电容器和单元晶体管的存储单元被布置在垂直单元结构中，被提供在DRAM的单元阵列中。 通过深度注入或浅注入和随后的硅的外延生长，形成掩埋源极/漏极层，电池晶体管的下部源极/漏极区域从该衬底源极/漏极层出现。 掩埋源极/漏极层的上边缘可以相对于单元晶体管的栅电极的下边缘对齐，并且这导致栅极/漏​​极电容的减小以及栅电极和漏电极之间的漏电流 较低的源极/漏极区域。 用于连接通道区域的主体连接板被施加到基板表面，并且接触孔被引入主体连接板。 单元晶体管的上源/漏区通过接触孔注入而形成。

公开(公告)号：US06861688B2

公开(公告)日：2005-03-01

申请号：US10288387

申请日：2002-11-05

Applicant: Dirk Manger ,  Till Schlösser

Inventor： Dirk Manger ,  Till Schlösser

IPC: H01L21/4763 ,  H01L21/768 ,  H01L21/8242 ,  H01L27/108 ,  H01L29/76

CPC classification number: H01L27/10888 ,  H01L27/10885

Abstract: A bit line configuration for contact-connecting at least one memory cell, in particular a DRAM memory cell, has bit lines disposed above the plane of the memory cell. A first bit line in a first bit line level is disposed below a second bit line in a second bit line level and the second bit line penetrates through the first bit line at at least one location of the first bit line for the purpose of producing a contact with the at least one memory cell at penetration locations. It is thus possible to provide space-saving structures, in particular sub-8F2 structures.

Abstract translation: 用于接触连接至少一个存储器单元，特别是DRAM存储单元的位线配置具有位于存储单元的平面之上的位线。 第一位线电平中的第一位线设置在第二位线电平中的第二位线下方，并且第二位线在第一位线的至少一个位置处穿过第一位线，以产生第 在穿透位置处与至少一个存储单元接触。 因此，可以提供节省空间的结构，特别是8F 2结构。

公开(公告)号：US20050001257A1

公开(公告)日：2005-01-06

申请号：US10777128

申请日：2004-02-13

Applicant: Till Schloesser ,  Dirk Manger ,  Bernd Goebel

Inventor： Till Schloesser ,  Dirk Manger ,  Bernd Goebel

IPC: H01L21/8239 ,  H01L21/8242 ,  H01L27/105 ,  H01L27/108

CPC classification number: H01L27/10876 ,  H01L27/10823

Abstract: In a substrate vertical transistor cells are formed and are arranged, in a transistor cell array, row by row in an x direction and column by column in a y direction. Lower source/drain regions of the transistor cells are connected to a common connection plate. Upper source/drain regions of the transistor cells impart a contact connection for instance to a storage capacitor of a DRAM memory cell. Active trenches running between the transistor cells with word lines are formed along the x direction. The word lines form gate electrodes in sections. A potential at the gate electrode controls a conductive channel in an active region arranged in each case between the upper and the lower source/drain connection region. According to the invention, the active regions of adjacent transistor cells are sections of a contiguous layer body and are connected to one another. An accumulation of charge carriers in the active region and floating body effects are avoided without increasing the area requirement of a transistor cell.

Abstract translation: 在衬底中，垂直晶体管单元被形成并且在晶体管单元阵列中沿x方向逐行排列并且沿y方向逐列地排列。 晶体管单元的较低源极/漏极区域连接到公共连接板。 晶体管单元的上部源极/漏极区域例如向DRAM存储单元的存储电容器提供接触连接。 沿着x方向形成在具有字线的晶体管单元之间运行的有源沟槽。 字线形成栅电极。 在栅电极处的电位控制在每个情况下布置在上下源极/漏极连接区域之间的有源区中的导电沟道。 根据本发明，相邻晶体管单元的有源区是连续层体的部分并彼此连接。 在不增加晶体管单元的面积要求的情况下避免了有源区中的电荷载流子的积累和浮体效应。