公开(公告)号：US07824995B2

公开(公告)日：2010-11-02

申请号：US12071717

申请日：2008-02-26

申请人： Takeshi Endo ,  Tsuyoshi Yamamoto ,  Eiichi Okuno

发明人： Takeshi Endo ,  Tsuyoshi Yamamoto ,  Eiichi Okuno

IPC分类号： H01L29/72

CPC分类号： H01L29/7828 ,  H01L21/049 ,  H01L29/045 ,  H01L29/0847 ,  H01L29/1608 ,  H01L29/51 ,  H01L29/66068

摘要： A SiC semiconductor device includes: a SiC substrate having a main surface; a channel region on the substrate; first and second impurity regions on upstream and downstream sides of the channel region, respectively; a gate on the channel region through a gate insulating film. The channel region for flowing current between the first and second impurity regions is controlled by a voltage applied to the gate. An interface between the channel region and the gate insulating film has a hydrogen concentration equal to or greater than 2.6×1020 cm−3. The interface provides a channel surface perpendicular to a (0001)-orientation plane.

摘要翻译： SiC半导体器件包括：具有主表面的SiC衬底; 衬底上的沟道区; 分别在通道区域的上游侧和下游侧的第一和第二杂质区域; 通过栅极绝缘膜在沟道区上形成栅极。 用于在第一和第二杂质区域之间流动电流的沟道区域由施加到栅极的电压来控制。 沟道区域和栅极绝缘膜之间的界面的氢浓度等于或大于2.6×1020cm-3。 界面提供垂直于（0001）取向平面的通道表面。

公开(公告)号：US07745276B2

公开(公告)日：2010-06-29

申请号：US12068263

申请日：2008-02-05

申请人： Eiichi Okuno ,  Hiroki Nakamura ,  Naohiro Suzuki

发明人： Eiichi Okuno ,  Hiroki Nakamura ,  Naohiro Suzuki

IPC分类号： H01L21/8234

CPC分类号： H01L29/7828 ,  H01L29/045 ,  H01L29/0615 ,  H01L29/0619 ,  H01L29/0657 ,  H01L29/1608 ,  H01L29/45 ,  H01L29/66068 ,  H01L29/7802 ,  H01L29/7811 ,  H01L29/7813

摘要： A method for manufacturing a SiC semiconductor device includes: preparing a SiC substrate having a (11-20)-orientation surface; forming a drift layer on the substrate; forming a base region in the drift layer; forming a first conductivity type region in the base region; forming a channel region on the base region to couple between the drift layer and the first conductivity type region; forming a gate insulating film on the channel region; forming a gate electrode on the gate insulating film; forming a first electrode to electrically connect to the first conductivity type region; and forming a second electrode on a backside of the substrate. The device controls current between the first and second electrodes by controlling the channel region. The forming the base region includes epitaxially forming a lower part of the base region on the drift layer.

摘要翻译： 一种制造SiC半导体器件的方法包括：制备具有（11-20）取向表面的SiC衬底; 在衬底上形成漂移层; 在漂移层中形成基极区; 在所述基底区域中形成第一导电类型区域; 在所述基极区上形成沟道区，以在所述漂移层和所述第一导电类型区之间耦合; 在沟道区上形成栅极绝缘膜; 在栅极绝缘膜上形成栅电极; 形成电连接到所述第一导电类型区域的第一电极; 以及在所述衬底的背面上形成第二电极。 该器件通过控制沟道区域来控制第一和第二电极之间的电流。 形成基极区域包括外延地形成漂移层上的基极区域的下部。

公开(公告)号：US20090166730A1

公开(公告)日：2009-07-02

申请号：US12318183

申请日：2008-12-23

申请人： Eiichi Okuno ,  Naohiro Suzuki ,  Nobuyuki Kato

发明人： Eiichi Okuno ,  Naohiro Suzuki ,  Nobuyuki Kato

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/7813 ,  H01L29/0623 ,  H01L29/1608 ,  H01L29/66068

摘要： A SiC semiconductor device includes: a substrate; a drift layer on the substrate; a trench on the drift layer; a base region in the drift layer sandwiching the trench; a channel between the base region and the trench; a source region in the base region sandwiching the trench via the channel; a gate electrode in the trench via a gate insulation film; a source electrode coupled with the source region; a drain electrode on the substrate opposite to the drift layer; and a bottom layer under the trench. An edge portion of the bottom layer under a corner of a bottom of the trench is deeper than a center portion of the bottom layer under a center portion of the bottom of the trench.

摘要翻译： SiC半导体器件包括：衬底; 衬底上的漂移层; 漂移层上的沟槽; 夹在沟槽中的漂移层中的基底区域; 基极区域和沟槽之间的沟道; 所述基极区域中的源极区域经由所述沟道夹持所述沟槽; 通过栅极绝缘膜在沟槽中的栅电极; 与源极区域耦合的源电极; 衬底上的与漂移层相反的漏电极; 和沟槽下方的底层。 在沟槽的底部的角部下方的底层的边缘部分比沟槽底部的中心部分下方的底层的中心部分更深。

公开(公告)号：US20090159898A1

公开(公告)日：2009-06-25

申请号：US12338151

申请日：2008-12-18

申请人： Hirokazu FUJIWARA ,  Masaki Konishi ,  Eiichi Okuno

发明人： Hirokazu FUJIWARA ,  Masaki Konishi ,  Eiichi Okuno

IPC分类号： H01L29/24 ,  H01L21/265

CPC分类号： H01L29/7813 ,  H01L29/04 ,  H01L29/1608 ,  H01L29/66068 ,  H01L29/872

摘要： A semiconductor device is provided in which the contact resistance of the interface between an electrode and the semiconductor substrate is reduced. The semiconductor device includes a 4H polytype SiC substrate, and an electrode formed on a surface of the substrate. A 3C polytype layer, which extends obliquely relative to the surface of the substrate and whose end portion at the substrate surface is in contact with the electrode, is formed at the surface of the substrate. The 3C polytype layer has a lower bandgap than 4H polytype. Hence, electrons present in the 4H polytype region pass through the 3C polytype layer and reach the electrode. More precisely, the width of the passageway of the electrons is determined by the thickness of the 3C polytype layer. Consequently, with this semiconductor device, in which the passageway of the electrons is narrow, the electrons are able to reach the electrode at a speed close to the theoretical value, by the quantum wire effect. In this way, the contact resistance can be reduced in the semiconductor device.

摘要翻译： 提供一种半导体器件，其中电极和半导体衬底之间的界面的接触电阻降低。 半导体器件包括4H多型SiC衬底和形成在衬底的表面上的电极。 形成在基板表面上相对于基板的表面倾斜地延伸并且其基板表面的端部与电极接触的3C多型层。 3C多型层具有比4H多型更低的带隙。 因此，存在于4H多型区域中的电子通过3C多型层并到达电极。 更准确地说，电子通道的宽度由3C多型层的厚度决定。 因此，通过电子通道窄的这种半导体器件，电子能够以接近理论值的速度通过量子线效应到达电极。 以这种方式，可以在半导体器件中降低接触电阻。

公开(公告)号：US07365363B2

公开(公告)日：2008-04-29

申请号：US11108906

申请日：2005-04-19

申请人： Jun Kojima ,  Takeshi Endo ,  Eiichi Okuno ,  Yoshihito Mitsuoka ,  Yoshiyuki Hisada ,  Hideo Matsuki

发明人： Jun Kojima ,  Takeshi Endo ,  Eiichi Okuno ,  Yoshihito Mitsuoka ,  Yoshiyuki Hisada ,  Hideo Matsuki

IPC分类号： H01L31/0312

CPC分类号： H01L29/66068 ,  H01L21/02024 ,  H01L29/045 ,  H01L29/513 ,  H01L29/517 ,  H01L29/7828

摘要： A silicon carbide semiconductor device includes: a semiconductor substrate having a principal surface and a backside surface; a drift layer disposed on the principal surface; a base region disposed on the drift layer; a source region disposed on the base region; a surface channel layer disposed on both of the drift layer and the base region for connecting between the source region and the drift layer; a gate insulation film disposed on the surface channel layer and including a high dielectric constant film; a gate electrode disposed on the gate insulation film; a source electrode disposed on the source region; and a backside electrode disposed on the backside surface.

摘要翻译： 碳化硅半导体器件包括：具有主表面和背面的半导体衬底; 设置在主表面上的漂移层; 设置在漂移层上的基极区域; 设置在所述基底区域上的源极区域; 设置在所述漂移层和所述基极区域两者上的表面沟道层，用于在所述源极区域和所述漂移层之间连接; 栅极绝缘膜，设置在所述表面沟道层上并且包括高介电常数膜; 设置在所述栅极绝缘膜上的栅电极; 源电极，其设置在所述源极区域上; 以及设置在所述背面上的背面电极。

公开(公告)号：US20070045631A1

公开(公告)日：2007-03-01

申请号：US11511236

申请日：2006-08-29

申请人： Takeshi Endo ,  Tsuyoshi Yamamoto ,  Jun Kawai ,  Kensaku Yamamoto ,  Eiichi Okuno

发明人： Takeshi Endo ,  Tsuyoshi Yamamoto ,  Jun Kawai ,  Kensaku Yamamoto ,  Eiichi Okuno

IPC分类号： H01L31/0312

CPC分类号： H01L21/049 ,  H01L29/045 ,  H01L29/0847 ,  H01L29/513 ,  H01L29/518 ,  H01L29/66068 ,  H01L29/78 ,  H01L29/7828 ,  H01L29/7838

摘要： A silicon carbide semiconductor device having a MOS structure includes: a substrate; a channel area in the substrate; a first impurity area; a second impurity area; a gate insulating film on the channel area; and a gate on the gate insulating film. The channel area provides an electric current path. The channel area and the gate insulating film have an interface therebetween. The interface includes a dangling bond, which is terminated by a hydrogen atom or a hydroxyl. The interface has a hydrogen concentration equal to or larger than 2.6×1020 cm−3.

摘要翻译： 具有MOS结构的碳化硅半导体器件包括：衬底; 衬底中的通道区域; 第一杂质区; 第二杂质区域; 通道区域上的栅极绝缘膜; 和栅极绝缘膜上的栅极。 通道区域提供电流通路。 沟道区域和栅极绝缘膜之间具有界面。 界面包括由氢原子或羟基封端的悬挂键。 界面的氢浓度等于或大于2.6×10 20 cm -3。

公开(公告)号：US06573534B1

公开(公告)日：2003-06-03

申请号：US09265582

申请日：1999-03-10

申请人： Rajesh Kumar ,  Tsuyoshi Yamamoto ,  Shoichi Onda ,  Mitsuhiro Kataoka ,  Kunihiko Hara ,  Eiichi Okuno ,  Jun Kojima

发明人： Rajesh Kumar ,  Tsuyoshi Yamamoto ,  Shoichi Onda ,  Mitsuhiro Kataoka ,  Kunihiko Hara ,  Eiichi Okuno ,  Jun Kojima

IPC分类号： H01L310312

CPC分类号： H01L29/7828 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/66068 ,  H01L29/7802 ,  H01L29/7838 ,  Y10S438/931

摘要： A semiconductor device, comprising: a semiconductor substrate comprising silicon carbide of a first conductivity type; a silicon carbide epitaxial layer of the first conductivity type; a first semiconductor region formed on the semiconductor substrate and comprising silicon carbide of a second conductivity type; a second semiconductor region formed on the first semiconductor region, comprising silicon carbide of the first conductivity type and separated from the semiconductor substrate of the first conductivity type by the first semiconductor region; a third semiconductor region formed on the semiconductor region, connected to the semiconductor substrate and the second semiconductor region, comprising silicon carbide of the first conductivity type, and of higher resistance than the semiconductor substrate; and a gate electrode formed on the third semiconductor region via an insulating layer; wherein the third semiconductor layer is depleted when no voltage is being applied to the gate electrode so that said semiconductor device has a normally OFF characteristic.

摘要翻译： 一种半导体器件，包括：包含第一导电类型的碳化硅的半导体衬底; 第一导电类型的碳化硅外延层; 形成在所述半导体衬底上并且包括第二导电类型的碳化硅的第一半导体区域; 形成在所述第一半导体区域上的第二半导体区域，包括所述第一导电类型的碳化硅并且通过所述第一半导体区域与所述第一导电类型的半导体衬底分离; 形成在所述半导体区域上的第三半导体区域，与所述半导体衬底和所述第二半导体区域连接，所述第二半导体区域包括所述第一导电型的碳化硅，并且具有比所述半导体衬底更高的电阻; 以及经由绝缘层形成在所述第三半导体区域上的栅电极; 其中当没有电压施加到所述栅电极时，所述第三半导体层被耗尽，使得所述半导体器件具有正常OFF特性。

公开(公告)号：US06221700B1

公开(公告)日：2001-04-24

申请号：US09362088

申请日：1999-07-28

申请人： Eiichi Okuno ,  Jun Kojima

发明人： Eiichi Okuno ,  Jun Kojima

IPC分类号： H01L2100

CPC分类号： H01L29/7827 ,  H01L21/046 ,  H01L29/1608 ,  H01L29/66068 ,  H01L29/7787 ,  H01L29/7828

摘要： A surface portion of a p type base region is made amorphous as an amorphous layer by implanting nitrogen ions which serve as impurities and ions which do not serve as impurities. After that, the amorphous layer is crystallized to have a specific crystal structure through solid-phase growth while disposing the impurities at lattice positions of the crystal structure. As a result, a surface channel layer is formed with a high activation rate of the impurities.

摘要翻译： p型基极区域的表面部分通过注入用作杂质的氮离子和不作为杂质的离子而被制成非晶态的非晶层。 此后，非晶层通过固相生长结晶化而具有特定的晶体结构，同时将杂质置于晶体结构的晶格位置。 结果，形成具有高的杂质活化率的表面通道层。

公开(公告)号：US08193564B2

公开(公告)日：2012-06-05

申请号：US12379076

申请日：2009-02-12

申请人： Naohiro Suzuki ,  Eiichi Okuno ,  Hideo Matsuki

发明人： Naohiro Suzuki ,  Eiichi Okuno ,  Hideo Matsuki

IPC分类号： H01L29/71

CPC分类号： H01L29/7813 ,  H01L29/0615 ,  H01L29/0619 ,  H01L29/0623 ,  H01L29/0634 ,  H01L29/0638 ,  H01L29/0661 ,  H01L29/0847 ,  H01L29/086 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/66068 ,  H01L29/7811 ,  H01L29/7828

摘要： A silicon carbide semiconductor device includes a substrate, a drift layer located on a first surface of the substrate, a base region located on the drift layer, a source region located on the base region, a trench penetrating the source region and the base region to the drift layer, a channel layer located in the trench, a gate insulating layer located on the channel layer, a gate electrode located on the gate insulating layer, a source electrode electrically coupled with the source region and the base region, a drain electrode located on a second surface of the substrate, and a deep layer. The deep layer is located under the base region, extends to a depth deeper than the trench and is formed along an approximately normal direction to a sidewall of the trench.

摘要翻译： 碳化硅半导体器件包括衬底，位于衬底的第一表面上的漂移层，位于漂移层上的基极区域，位于基极区域上的源极区域，穿透源极区域和基极区域的沟槽 漂移层，位于沟槽中的沟道层，位于沟道层上的栅极绝缘层，位于栅极绝缘层上的栅电极，与源区和基极区电耦合的源电极，位于 在衬底的第二表面上和深层。 深层位于基底区域下方，延伸到比沟槽更深的深度，并且沿着大致正常的方向形成在沟槽的侧壁上。

公开(公告)号：US07713805B2

公开(公告)日：2010-05-11

申请号：US11976217

申请日：2007-10-23

申请人： Hiroki Nakamura ,  Hiroyuki Ichikawa ,  Eiichi Okuno

发明人： Hiroki Nakamura ,  Hiroyuki Ichikawa ,  Eiichi Okuno

IPC分类号： H01L21/336 ,  H01L21/8234

CPC分类号： H01L29/7828 ,  H01L21/049 ,  H01L29/41741 ,  H01L29/45 ,  H01L29/66068

摘要： A method of manufacturing a silicon carbide semiconductor device having a MOS structure includes preparing a substrate made of silicon carbide, and forming a channel region, a first impurity region, a second impurity region, a gate insulation layer, and a gate electrode to form a semiconductor element on the substrate. In addition, a film is formed on the semiconductor element to provide a material of an interlayer insulation layer, and a reflow process is performed at a temperature about 700° C. or over in an wet atmosphere so that the interlayer insulation layer is formed from the film and an edge portion of the gate electrode is rounded and oxidized.

摘要翻译： 制造具有MOS结构的碳化硅半导体器件的方法包括制备由碳化硅制成的衬底，并形成沟道区，第一杂质区，第二杂质区，栅绝缘层和栅电极，以形成 半导体元件。 此外，在半导体元件上形成膜以提供层间绝缘层的材料，并且在湿气氛中在约700℃或更高的温度下进行回流工艺，使得层间绝缘层由 该膜和栅电极的边缘部分被圆化并氧化。