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21.发明申请CMOS STORAGE DEVICES CONFIGURABLE IN HIGH PERFORMANCE MODE OR RADIATION TOLERANT MODE 有权CMOS存储设备可配置在高性能模式或辐射容限模式公开(公告)号：US20090059657A1
公开(公告)日：2009-03-05
申请号：US11845170
申请日：2007-08-27
CPC分类号： G11C11/4125 , G11C13/0004
摘要： A radiation tolerant circuit, structure of the circuit and method of autonomic radiation event device protection. The circuit includes a charge storage node connected to a resistor, the resistor comprising a material having an amorphous state and a crystalline state, the amorphous state having a higher resistance than the crystalline state, the material reversibly convertible between the amorphous state and the crystalline state by application of heat; an optional resistive heating element proximate to the resistor; and means for writing data to the charge storage node and means for reading data from the charge storage node.
摘要翻译： 辐射耐受电路，电路结构及自主辐射事件装置保护方法。 电路包括连接到电阻器的电荷存储节点，该电阻器包括具有非晶状态和结晶状态的材料，非晶状态具有比结晶状态更高的电阻，该材料可在非晶状态和结晶态之间可逆地转换 通过应用热量; 靠近电阻器的可选电阻加热元件; 以及用于向电荷存储节点写入数据的装置和用于从电荷存储节点读取数据的装置。
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22.发明授权Capacitor below the buried oxide of SOI CMOS technologies for protection against soft errors 失效SOI CMOS技术的掩埋氧化物之下的电容器，用于防止软错误公开(公告)号：US07315075B2
公开(公告)日：2008-01-01
申请号：US10905906
申请日：2005-01-26
IPC分类号： H01L29/00 , H01L29/76 , H01L29/94 , H01L31/062
CPC分类号： H01L27/1203 , H01L29/92
摘要： Disclosed is a semiconductor structure that incorporates a capacitor for reducing the soft error rate of a device within the structure. The multi-layer semiconductor structure includes an insulator-filled deep trench isolation structure that is formed through an active silicon layer, a first insulator layer, and a first bulk layer and extends to a second insulator layer. The resulting isolated portion of the first bulk layer defines the first capacitor plate. A portion of the second insulator layer that is adjacent the first capacitor plate functions as the capacitor dielectric. Either the silicon substrate or a portion of a second bulk layer that is isolated by a third insulator layer and another deep trench isolation structure can function as the second capacitor plate. A first capacitor contact couples, either directly or via a wire array, the first capacitor plate to a circuit node of the device in order to increase the critical charge, Qcrit, of the circuit node.
摘要翻译： 公开了一种包含用于降低结构内的器件的软错误率的电容器的半导体结构。 多层半导体结构包括通过有源硅层，第一绝缘体层和第一体层形成并延伸到第二绝缘体层的绝缘体填充的深沟槽隔离结构。 所形成的第一体层的隔离部分限定第一电容器板。 与第一电容器板相邻的第二绝缘体层的一部分用作电容器电介质。 硅衬底或由第三绝缘体层和另一个深沟槽隔离结构隔离的第二体层的一部分可以用作第二电容器板。 第一电容器触点直接地或经由线阵列将第一电容器板耦合到器件的电路节点，以便增加电路节点的临界电荷Qcrit。
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公开(公告)号：US20070268736A1
公开(公告)日：2007-11-22
申请号：US11419341
申请日：2006-05-19
申请人： Ethan H. Cannon , Alvin W. Strong
发明人： Ethan H. Cannon , Alvin W. Strong
IPC分类号： G11C11/00
CPC分类号： H01L23/345 , H01L2924/0002 , H01L2924/00
摘要： An on-chip heater and methods for fabrication thereof and use thereof provide that the heater is located within an isolation region that in turn is located within a semiconductor substrate. The heater has a thermal output capable or raising the semiconductor substrate to a temperature of at least about 200° C. The heater may be used for thermally annealing trapped charges within dielectric layers within the semiconductor structure.
摘要翻译： 片上加热器及其制造方法及其用途提供了加热器位于隔离区域内，隔离区域又位于半导体衬底内。 该加热器具有使半导体衬底能够或将其升高至至少约200℃的热输出。该加热器可用于对半导体结构内的电介质层内的俘获电荷进行热退火。
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公开(公告)号：US07064414B2
公开(公告)日：2006-06-20
申请号：US10904483
申请日：2004-11-12
IPC分类号： H01L29/00
CPC分类号： H01L24/80 , H01L23/345 , H01L2924/01005 , H01L2924/01006 , H01L2924/01033 , H01L2924/01082 , H01L2924/14 , H01L2924/00
摘要： A structure and associated method for annealing a trapped charge from a semiconductor device. The semiconductor structure comprises a substrate and a first heating element. The substrate comprises a bulk layer, an insulator layer and a device layer. The first heating element is formed within the bulk layer. A first side of the first heating element is adjacent to a first portion of the insulator layer. The first heating element is adapted to be selectively activated to generate thermal energy to heat the first portion of the insulator layer and anneal a trapped electrical charge from the first portion of the insulator layer.
摘要翻译： 一种从半导体器件退火俘获电荷的结构和相关方法。 半导体结构包括基板和第一加热元件。 衬底包括体层，绝缘体层和器件层。 第一加热元件形成在本体层内。 第一加热元件的第一侧与绝缘体层的第一部分相邻。 第一加热元件适于被选择性地激活以产生热能来加热绝缘体层的第一部分并且从绝缘体层的第一部分退火被俘获的电荷。
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公开(公告)号：US08647909B2
公开(公告)日：2014-02-11
申请号：US13357728
申请日：2012-01-25
IPC分类号： H01L21/00
CPC分类号： H01L31/115 , H01L23/552 , H01L23/556 , H01L25/0657 , H01L2924/0002 , H01L2924/00
摘要： An array of radiation sensors or detectors is integrated within a three-dimensional semiconductor IC. The sensor array is located relatively close to the device layer of a circuit (e.g., a microprocessor) to be protected from the adverse effects of the ionizing radiation particles. As such, the location where the radiation particles intersect the device layer can be calculated with coarse precision (e.g., to within 10 s of microns).
摘要翻译： 辐射传感器或检测器阵列集成在三维半导体IC内。 传感器阵列相对靠近电路（例如，微处理器）的器件层定位，以防止电离辐射粒子的不利影响。 因此，辐射粒子与器件层相交的位置可以用粗精度（例如，在10微米以内）来计算。
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26.发明申请DEEP TRENCH CAPACITOR FOR SOI CMOS DEVICES FOR SOFT ERROR IMMUNITY 有权用于软错误免疫的SOI CMOS器件的深度TRENCH电容器公开(公告)号：US20110177660A1
公开(公告)日：2011-07-21
申请号：US13075271
申请日：2011-03-30
IPC分类号： H01L21/8242
CPC分类号： H01L27/1203 , H01L21/84 , H01L27/0629 , H01L27/10861 , H01L29/66181
摘要： A semiconductor structure is disclosed. The semiconductor structure includes an active semiconductor layer, a semiconductor device having a gate disposed on top of the active semiconductor layer, and source and drain regions and a body/channel region disposed within the active semiconductor layer, an insulator layer having a first and second side, the first side being adjacent to the active semiconductor layer, a substrate disposed adjacent to the second side of the insulator layer, a deep trench capacitor disposed under the body/channel region of the semiconductor device. The deep trench capacitor electrically connects with and contacts the body/channel region of the semiconductor device, and is located adjacent to the gate of the semiconductor device. The semiconductor structure increases a critical charge Qcrit, thereby reducing a soft error rate (SER) of the semiconductor device.
摘要翻译： 公开了半导体结构。 半导体结构包括有源半导体层，具有设置在有源半导体层顶部的栅极的半导体器件以及设置在有源半导体层内的源极和漏极区域以及主体/沟道区域，具有第一和第二 所述第一侧与所述有源半导体层相邻，与所述绝缘体层的所述第二侧相邻配置的衬底，设置在所述半导体器件的所述主体/沟道区域下方的深沟槽电容器。 深沟槽电容器与半导体器件的主体/沟道区电连接并接触半导体器件的主体/沟道区，并且位于半导体器件的栅极附近。 半导体结构增加了临界电荷Qcrit，从而降低了半导体器件的软错误率（SER）。
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27.发明申请公开(公告)号：US20110025372A1
公开(公告)日：2011-02-03
申请号：US12511207
申请日：2009-07-29
IPC分类号： H03K19/003 , H03K3/289 , G06F17/50
CPC分类号： G11C5/005 , G11C7/02 , H03K3/0375 , H03K3/356121 , H03K17/693
摘要： The different advantageous embodiments provide an integrated circuit comprising a number of latches and a number of filters. Each latch in the number of latches has a plurality of inputs and a plurality of storage nodes. The plurality of storage nodes includes a number of pairs of circuit nodes that form a number of upsettable circuit node pairs. Each input of the plurality of inputs is connected to a corresponding storage node in the plurality of storage nodes. Each filter in the number of filters has an input and a plurality of outputs. Each of the plurality of outputs is connected to a corresponding input of the plurality of inputs of a latch in the number of latches. Each filter in the number of filters is located between two circuit nodes forming an upsettable circuit node pair of the latch in the number of latches to increase critical node spacing.
摘要翻译： 不同的有利实施例提供了包括多个锁存器和多个滤波器的集成电路。 锁存器数量中的每个锁存器具有多个输入和多个存储节点。 多个存储节点包括形成多个可压缩电路节点对的多对电路节点。 多个输入的每个输入连接到多个存储节点中的对应的存储节点。 多个滤波器中的每个滤波器具有输入和多个输出。 多个输出中的每一个连接到锁存器数量的锁存器的多个输入的相应输入。 滤波器数量中的每个滤波器位于两个电路节点之间，形成锁存器数量的锁存器的可升高电路节点对以增加关键节点间隔。
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28.发明授权Device structures with a self-aligned damage layer and methods for forming such device structures 失效具有自对准损伤层的装置结构和用于形成这种装置结构的方法公开(公告)号：US07795679B2
公开(公告)日：2010-09-14
申请号：US12178766
申请日：2008-07-24
申请人： Ethan H. Cannon , Fen Chen
发明人： Ethan H. Cannon , Fen Chen
IPC分类号： H01L31/0392 , H01L21/8238 , H01L21/336
CPC分类号： H01L29/0653 , H01L21/26506 , H01L29/6659 , H01L29/66659 , H01L29/7842 , H01L29/7848
摘要： Device structures with a self-aligned damage layer and methods of forming such device structures. The device structure first and second doped regions of a first conductivity type defined in the semiconductor material of a substrate. A third doped region of opposite conductivity type laterally separates the first doped region from the second doped region. A gate structure is disposed on a top surface of the substrate and has a vertically stacked relationship with the third doped region. A first crystalline damage layer is defined within the semiconductor material of the substrate. The first crystalline damage layer has a first plurality of voids surrounded by the semiconductor material of the substrate. The first doped region is disposed vertically between the first crystalline damage layer and the top surface of the substrate. The first crystalline damage layer does not extend laterally into the third doped region.
摘要翻译： 具有自对准损伤层的装置结构和形成这种装置结构的方法。 该器件结构是限定在衬底的半导体材料中的第一导电类型的第一和第二掺杂区域。 相反导电类型的第三掺杂区域将第一掺杂区域与第二掺杂区域横向分离。 栅极结构设置在衬底的顶表面上，并且与第三掺杂区域具有垂直堆叠的关系。 第一晶体损伤层被限定在衬底的半导体材料内。 第一晶体损伤层具有由衬底的半导体材料包围的第一多个空隙。 第一掺杂区域垂直地设置在第一晶体损伤层和衬底的顶表面之间。 第一晶体损伤层不横向延伸到第三掺杂区域。
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公开(公告)号：US07791123B2
公开(公告)日：2010-09-07
申请号：US12045190
申请日：2008-03-10
IPC分类号： H01L27/108
CPC分类号： H01L29/66181 , G11C5/005 , H01L21/765 , H01L27/0629 , H01L27/11 , H01L29/945
摘要： A deep trench containing a doped semiconductor fill portion having a first conductivity type doping and surrounded by a buried plate layer having a second conductivity type doping at a lower portion is formed in a semiconductor layer having a doping of the first conductivity type. A doped well of the second conductivity type abutting the buried plate layer is formed. The doped semiconductor fill portion functions as a temporary reservoir for electrical charges of the first conductivity type that are generated by a radiation particle, and the buried plate layer functions as a temporary reservoir for electrical charges of the second conductivity type. The buried plate layer and the doped semiconductor fill portion forms a capacitor, and provides protection from soft errors to devices formed in the semiconductor layer or the doped well.
摘要翻译： 在具有第一导电类型的掺杂的半导体层中形成包含掺杂半导体填充部分的深沟槽，该掺杂半导体填充部分具有第一导电类型掺杂并被由下部具有第二导电类型掺杂的掩埋板包围。 形成与掩埋板层相邻的第二导电类型的掺杂阱。 掺杂半导体填充部分用作由辐射颗粒产生的第一导电类型的电荷的临时储存器，并且掩埋板层用作第二导电类型的电荷的临时储存器。 掩埋板层和掺杂半导体填充部分形成电容器，并且提供对软错误的保护以防止在半导体层或掺杂阱中形成的器件。
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公开(公告)号：US20100200953A1
公开(公告)日：2010-08-12
申请号：US12766342
申请日：2010-04-23
申请人： Ethan H. Cannon , Alvin W. Strong
发明人： Ethan H. Cannon , Alvin W. Strong
CPC分类号： H01L23/345 , H01L2924/0002 , H01L2924/00
摘要： An on-chip heater and methods for fabrication thereof and use thereof provide that the heater is located within an isolation region that in turn is located within a semiconductor substrate. The heater has a thermal output capable or raising the semiconductor substrate to a temperature of at least about 200° C. The heater may be used for thermally annealing trapped charges within dielectric layers within the semiconductor structure.
摘要翻译： 片上加热器及其制造方法及其用途提供了加热器位于隔离区域内，隔离区域又位于半导体衬底内。 该加热器具有使半导体衬底能够或将其升高至至少约200℃的热输出。该加热器可用于对半导体结构内的电介质层内的俘获电荷进行热退火。
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