公开(公告)号：US20050262336A1

公开(公告)日：2005-11-24

申请号：US10850783

申请日：2004-05-21

申请人： Naveen Cherukuri ,  Sanjay Dabral ,  David Dunning ,  Tim Frodsham ,  Theodore Schoenborn

发明人： Naveen Cherukuri ,  Sanjay Dabral ,  David Dunning ,  Tim Frodsham ,  Theodore Schoenborn

IPC分类号： G06F15/177 ,  H04L29/08

CPC分类号： H04L69/32

摘要： A method for effecting an in-band reset of the physical layers of two agents interconnected through a link-based interconnection scheme. In accordance with one embodiment of the invention, a first of the two agents ceases its forwarded clock to initiate the in-band reset. Upon realization of the cessation, a second agent ceases its forwarded clock and proceeds to a reset state. The first agent then proceeds to a reset state. Subsequently, after waiting a specified period of time, both agents proceed with a re-initialization of the physical layer. In accordance with one embodiment of the invention, the re-initialization of the physical layer is effected without impacting other layers of the interconnection hierarchy.

摘要翻译： 一种用于实现通过基于链路的互连方案互联的两个代理的物理层的带内复位的方法。 根据本发明的一个实施例，两个代理中的第一个停止其转发的时钟以启动带内复位。 在停止实现时，第二代理程序停止其转发的时钟并进入复位状态。 然后第一个代理进入复位状态。 随后，等待指定的时间段后，两个代理进行物理层的重新初始化。 根据本发明的一个实施例，实现物理层的重新初始化而不影响互连层次结构的其他层。

公开(公告)号：US06922071B2

公开(公告)日：2005-07-26

申请号：US10330598

申请日：2002-12-27

申请人： Sanjay Dabral ,  Santanu Chaudhuri

发明人： Sanjay Dabral ,  Santanu Chaudhuri

IPC分类号： H03K19/173 ,  H03K17/16

CPC分类号： H03K19/1732

摘要： A method for setting multiple chip parameters using one IC terminal is described. The chip comprises a first circuit coupled to the pin for setting a first parameter. A second circuit coupled to the pin sets a second parameter. In addition, a third circuit coupled to the pin sets a third parameter of the chip.

摘要翻译： 描述使用一个IC终端设置多个芯片参数的方法。 芯片包括耦合到引脚的第一电路以设置第一参数。 耦合到引脚的第二电路设置第二参数。 此外，耦合到引脚的第三电路设置芯片的第三参数。

公开(公告)号：US06561410B2

公开(公告)日：2003-05-13

申请号：US10116503

申请日：2002-04-03

申请人： Sanjay Dabral ,  Ming Zeng

发明人： Sanjay Dabral ,  Ming Zeng

IPC分类号： B23K3102

CPC分类号： H05K1/0246 ,  G06F13/4086 ,  H05K1/0298 ,  H05K1/181 ,  H05K2201/09236 ,  H05K2201/10545 ,  H05K2201/10689 ,  H05K2201/10734 ,  Y02P70/611 ,  Y10T29/49144 ,  Y10T29/49155

摘要： A multi layer printed circuit board with a 3-load topology is disclosed. First, second, and third integrated circuit (IC) printed wiring board packages having first, second, and third sets of terminals respectively are mounted on opposite sides of the board so that the second set of terminals are directly opposite the third set of terminals. Each package contains an IC die coupled to the respective set of terminals. The IC die in the first package is substantially identical to the one contained in the second package, and different than the one contained in the third package. For improved fanout of the metal lines that interconnect the first package to the second and third packages, each of the first, second, and third sets of terminals in the packages is arranged in substantially a U-shape. Each set of terminals has the same set of signal assignments of a parallel bus implemented by metal lines in the board. The 3-load topology is particularly useful for personal computer motherboard units having twin processors and a bridge chip set, yielding a motherboard having significantly lower number of metal layers, a faster bus and significantly improved noise margin, all with high density IC packages on a wide parallel bus.

公开(公告)号：US06453422B1

公开(公告)日：2002-09-17

申请号：US09470686

申请日：1999-12-23

申请人： Sanjay Dabral ,  Stephen R. Mooney ,  T. Zale Schoenborn ,  Sam E. Calvin ,  Tim Frodsham

发明人： Sanjay Dabral ,  Stephen R. Mooney ,  T. Zale Schoenborn ,  Sam E. Calvin ,  Tim Frodsham

IPC分类号： G06F126

CPC分类号： H04L12/40032 ,  H04L12/4013

摘要： According to an embodiment of the invention a circuit that is to be coupled to a reference voltage line. The circuit includes a noise coupling circuit that is to couple noise from the circuit to a reference voltage line based upon whether a driver is driving a data line.

摘要翻译： 根据本发明的实施例，要耦合到参考电压线的电路。 电路包括噪声耦合电路，其基于驱动器是否驱动数据线，将来自电路的噪声耦合到参考电压线。

公开(公告)号：US06373715B1

公开(公告)日：2002-04-16

申请号：US09467300

申请日：1999-12-17

申请人： Ming Zeng ,  Sanjay Dabral

发明人： Ming Zeng ,  Sanjay Dabral

IPC分类号： H05K702

CPC分类号： H05K1/181 ,  H05K1/0298 ,  H05K7/1459 ,  H05K2201/09236 ,  H05K2201/10545 ,  H05K2201/10689 ,  H05K2201/10734 ,  Y02P70/611

摘要： A topology for mounting processors on opposite sides of a printed circuit board (PCB) orients rows of processor connection pins parallel to the bus orientation within the PCB and defines a relative 180 degree orientation between the opposing processors.

摘要翻译： 用于将处理器安装在印刷电路板（PCB）的相对侧上的拓扑结构将排列的处理器连接引脚平行于PCB内的总线方向定位，并定义相对的处理器之间的相对180度取向。

公开(公告)号：US6090650A

公开(公告)日：2000-07-18

申请号：US940303

申请日：1997-09-30

申请人： Sanjay Dabral ,  Krishna Seshan

发明人： Sanjay Dabral ,  Krishna Seshan

IPC分类号： G06F13/40 ,  H01L21/8234 ,  H01L21/8238 ,  H01L29/423 ,  H03L7/00 ,  H01L21/337

CPC分类号： H03L7/00 ,  G06F13/4072 ,  H01L21/823418 ,  H01L21/823437 ,  H01L21/823828 ,  H01L29/4238 ,  H01L2924/0002

摘要： A method of reducing random, processing-induced timing variations in a field effect transistor device includes providing a semiconductor substrate having an active area, and forming a transistor having a gate over a portion of the active area, the gate having a first leg and a second leg. In a further aspect, a method of improving the timing skew of critically-matched circuits is presented. In a still further aspect of the invention, a field effect transistor and an integrated circuit device that can be used to improve timing robustness in the presence of random fabrication- or process-induced variations are presented.

公开(公告)号：US08914541B2

公开(公告)日：2014-12-16

申请号：US13240546

申请日：2011-09-22

申请人： Naveen Cherukuri ,  Aaron T. Spink ,  Phanindra Mannaya ,  Tim Frodsham ,  Jeffrey R. Wilcox ,  Sanjay Dabral ,  David Dunning ,  Theodore Z. Schoenborn

发明人： Naveen Cherukuri ,  Aaron T. Spink ,  Phanindra Mannaya ,  Tim Frodsham ,  Jeffrey R. Wilcox ,  Sanjay Dabral ,  David Dunning ,  Theodore Z. Schoenborn

IPC分类号： G06F15/16 ,  G06F13/42

CPC分类号： H04L67/141 ,  G06F13/4265 ,  H04L65/60 ,  Y02D10/14 ,  Y02D10/151

摘要： Systems and methods of managing a link provide for receiving a remote width capability during a link initialization, the remote width capability corresponding to a remote port. A link between a local port and the remote port is operated at a plurality of link widths in accordance with the remote width capability.

摘要翻译： 管理链路的系统和方法提供了在链路初始化期间接收远程宽度能力，即对应于远程端口的远程宽度能力。 根据远程宽度能力，本地端口和远程端口之间的链路以多个链路宽度进行操作。

公开(公告)号：US20140156892A1

公开(公告)日：2014-06-05

申请号：US13913774

申请日：2013-06-10

申请人： Tim Frodsham ,  Michael J. Tripp ,  David J. O'Brien ,  Navada Herur Muraleedhara ,  Naveen Cherukuri ,  Sanjay Dabral ,  David S. Dunning ,  Theodore Z. Schoenborn

发明人： Tim Frodsham ,  Michael J. Tripp ,  David J. O'Brien ,  Navada Herur Muraleedhara ,  Naveen Cherukuri ,  Sanjay Dabral ,  David S. Dunning ,  Theodore Z. Schoenborn

IPC分类号： G06F1/06 ,  G06F13/362

CPC分类号： G06F1/06 ,  G06F13/362 ,  H04L43/50

摘要： A link latency management for a high-speed point-to-point network (pTp) is described The link latency management facilitates calculating latency of a serial interface by tracking a round trip delay of a header that contains latency information. Therefore, the link latency management facilitates testers, logic analyzers, or test devices to accurately measure link latency for a point-to-point architecture utilizing a serial interface.

摘要翻译： 描述了用于高速点对点网络（pTp）的链路延迟管理。链路延迟管理有助于通过跟踪包含延迟信息的报头的往返延迟来计算串行接口的延迟。 因此，链路延迟管理便于测试人员，逻辑分析仪或测试设备使用串行接口准确测量点对点架构的链路延迟。

公开(公告)号：US08046488B2

公开(公告)日：2011-10-25

申请号：US10850851

申请日：2004-05-21

申请人： Naveen Cherukuri ,  Aaron T. Spink ,  Phanindra Mannava ,  Tim Frodsham ,  Jeffrey R. Wilcox ,  Sanjay Dabral ,  David Dunning ,  Theodore Z. Schoenborn

发明人： Naveen Cherukuri ,  Aaron T. Spink ,  Phanindra Mannava ,  Tim Frodsham ,  Jeffrey R. Wilcox ,  Sanjay Dabral ,  David Dunning ,  Theodore Z. Schoenborn

IPC分类号： G06F15/16

CPC分类号： H04L67/141 ,  G06F13/4265 ,  H04L65/60 ,  Y02D10/14 ,  Y02D10/151

摘要： Systems and methods of managing a link provide for receiving a remote width capability during a link initialization, the remote width capability corresponding to a remote port. A link between a local port and the remote port is operated at a plurality of link widths in accordance with the remote width capability.

摘要翻译： 管理链路的系统和方法提供了在链路初始化期间接收远程宽度能力，即对应于远程端口的远程宽度能力。 根据远程宽度能力，本地端口和远程端口之间的链路以多个链路宽度进行操作。

公开(公告)号：US07957428B2

公开(公告)日：2011-06-07

申请号：US10850809

申请日：2004-05-21

申请人： Maurice B. Steinman ,  Rahul R. Shah ,  Naveen Cherukuri ,  Aaron T. Spink ,  Allen J. Baum ,  Sanjay Dabral ,  Tim Frodsham ,  David S. Dunning ,  Theodore Z. Schoenborn

发明人： Maurice B. Steinman ,  Rahul R. Shah ,  Naveen Cherukuri ,  Aaron T. Spink ,  Allen J. Baum ,  Sanjay Dabral ,  Tim Frodsham ,  David S. Dunning ,  Theodore Z. Schoenborn

IPC分类号： H04J3/04

CPC分类号： G06F13/4018 ,  G06F13/4009 ,  Y02D10/14 ,  Y02D10/151

摘要： Embodiments of the invention provide an algorithm for dividing a link into one or more reduced-width links. For one embodiment of the invention, a multiplexing scheme is employed to effect a bit transmission order required by a particular cyclic redundancy check. The multiplexed output bits are then swizzled on-chip to reduce on-board routing congestion.

摘要翻译： 本发明的实施例提供了一种用于将链路划分成一个或多个缩小宽度链路的算法。 对于本发明的一个实施例，采用复用方案来实现特定循环冗余校验所需的位传输顺序。 多路复用的输出位随后在芯片上转动，以减少车载路由拥塞。