公开(公告)号：US20200002813A1

公开(公告)日：2020-01-02

申请号：US16023470

申请日：2018-06-29

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Jiehui Shu ,  John H. Zhang ,  Jinping Liu

IPC: C23C16/455

Abstract: Systems and methods for depositing a material by atomic layer deposition. A first gas distribution unit is configured to provide a first precursor to a first zone inside a reaction chamber. A second gas distribution unit is configured to provide a second precursor to a second zone inside the reaction chamber. A substrate support is arranged to hold the substrates inside the reaction chamber. The substrate support is configured to linearly move the substrates relative to the reaction chamber from the first zone to the second zone as part of a cyclic deposition cycle of an atomic layer deposition process depositing the film on each of the substrates held by the substrate support.

公开(公告)号：US20190229019A1

公开(公告)日：2019-07-25

申请号：US15878081

申请日：2018-01-23

Applicant: GLOBALFOUNDRIES INC.

Inventor： Jiehui Shu ,  Xusheng Wu ,  Haigou Huang ,  John H. Zhang ,  Pei Liu ,  Laertis Economikos

IPC: H01L21/8234 ,  H01L27/088 ,  H01L29/49 ,  H01L23/535 ,  H01L21/768

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a contact over an active gate structure and methods of manufacture. The structure includes: an active gate structure composed of conductive material located between sidewall material; an upper sidewall material above the sidewall material, the upper sidewall material being different material than the sidewall material; and a contact structure in electrical contact with the conductive material of the active gate structure. The contact structure is located between the sidewall material and between the upper sidewall material.

公开(公告)号：US20190148494A1

公开(公告)日：2019-05-16

申请号：US15814724

申请日：2017-11-16

Applicant: GLOBALFOUNDRIES INC.

Inventor： Ruilong Xie ,  Lars Liebmann ,  Daniel Chanemougame ,  Chanro Park ,  John H. Zhang ,  Steven Bentley ,  Hui Zang

IPC: H01L29/10 ,  H01L29/78 ,  H01L27/24 ,  H01L21/8234

Abstract: A first vertical field effect transistor (VFET) and a second VFET are formed on a substrate. The VFETs are parallel and adjacent to one another, and each comprises: a fin-shaped semiconductor; a lower source/drain (S/D) element; an upper S/D element; and a gate conductor. A portion of a gate conductor of the second VFET that is positioned over a lower S/D element of the second VFET is removed to leave a trench. An isolation spacer is formed to contact the gate conductor of the second VFET in a first portion of the trench. A lower S/D contact of the second VFET is formed on the lower S/D element of the second VFET in a second portion of the trench, a lower S/D contact of the first VFET is formed to a lower S/D element of the first VFET, and contacts are formed.

公开(公告)号：US10269812B1

公开(公告)日：2019-04-23

申请号：US15814724

申请日：2017-11-16

Applicant: GLOBALFOUNDRIES INC.

Inventor： Ruilong Xie ,  Lars Liebmann ,  Daniel Chanemougame ,  Chanro Park ,  John H. Zhang ,  Steven Bentley ,  Hui Zang

IPC: H01L27/112 ,  H01L29/10 ,  H01L21/8234 ,  H01L27/24 ,  H01L29/78 ,  H01L29/808 ,  H01L45/00 ,  H01L29/66 ,  H01L29/06 ,  H01L23/522 ,  H01L21/02

Abstract: A first vertical field effect transistor (VFET) and a second VFET are formed on a substrate. The VFETs are parallel and adjacent to one another, and each comprises: a fin-shaped semiconductor; a lower source/drain (S/D) element; an upper S/D element; and a gate conductor. A portion of a gate conductor of the second VFET that is positioned over a lower S/D element of the second VFET is removed to leave a trench. An isolation spacer is formed to contact the gate conductor of the second VFET in a first portion of the trench. A lower S/D contact of the second VFET is formed on the lower S/D element of the second VFET in a second portion of the trench, a lower S/D contact of the first VFET is formed to a lower S/D element of the first VFET, and contacts are formed.

公开(公告)号：US10249496B2

公开(公告)日：2019-04-02

申请号：US15587597

申请日：2017-05-05

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Jiehui Shu ,  Xusheng Yu ,  John H. Zhang ,  Xiaoqiang Zhang

IPC: H01L21/033 ,  H01L23/525 ,  H01L23/532 ,  H01L21/311

Abstract: Interconnect structures and methods of fabricating an interconnect structure. A first mandrel line, a second mandrel line, and a non-mandrel line between the first mandrel line and the second mandrel line are provided. A first sidewall spacer is formed adjacent to a section of the first mandrel line and is arranged between the section of the first mandrel line and the non-mandrel line. A first cut is formed that extends partially across the non-mandrel line adjacent to the first spacer to narrow a section of the non-mandrel line. The section of the first mandrel line is removed selective to the first sidewall spacer to form a second cut. An interconnect is formed using the non-mandrel line. The interconnect includes a narrowed section coinciding with a location of the narrowed section of the non-mandrel line.

公开(公告)号：US09812365B1

公开(公告)日：2017-11-07

申请号：US15286117

申请日：2016-10-05

Applicant: GLOBALFOUNDRIES Inc.

Inventor： John H. Zhang ,  Haigou Huang ,  Xusheng Wu ,  Ruilong Xie ,  Stan Tsai

IPC: H01L21/8234 ,  H01L21/02 ,  H01L29/66 ,  H01L21/311 ,  H01L21/3105

CPC classification number: H01L21/823437 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/31056 ,  H01L21/31144 ,  H01L29/66545 ,  H01L29/66636

Abstract: One illustrative method disclosed includes, among other things, forming a plurality of gates above a substrate, each of the gates comprising a gate structure and a first layer of a first insulating material positioned on an upper surface of the gate structure, and forming a second layer of a second insulating material above insulating material positioned above the substrate between the laterally spaced apart gates, wherein the first insulating material and the second insulating material are selectively etchable relative to one another. The method may also include selectively removing a portion of the first layer to thereby expose a portion of the gate structure of at least one of the gates, selectively removing the exposed portion of the gate structure so as to thereby define a gate-cut cavity, and forming an insulating gate-cut structure in the gate-cut cavity.

公开(公告)号：US09741613B1

公开(公告)日：2017-08-22

申请号：US15175308

申请日：2016-06-07

Applicant: GLOBALFOUNDRIES Inc.

Inventor： John H. Zhang ,  Carl J. Radens ,  Lawrence A. Clevenger

IPC: H01L21/302 ,  H01L21/461 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532

CPC classification number: H01L21/76897 ,  H01L21/76808 ,  H01L21/76816

Abstract: A method for producing self-aligned line end vias and the resulting device are provided. Embodiments include forming trenches in a dielectric layer; filling the trenches with a sacrificial layer; forming and etching a block mask over sacrificial layers to form a cut area over a portion of the trenches; forming spacers at sides of the cut area; removing the sacrificial layer from the portion of the trenches; forming a mask in the cut area and the portion of trenches, the mask selected from a HDP oxide, SiC or SiCNH; selectively etching the spacers; and selectively etching the sacrificial layer and the dielectric layer by RIE to form SAVs.