公开(公告)号：US09293363B2

公开(公告)日：2016-03-22

申请号：US14805443

申请日：2015-07-21

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Sunil K. Singh ,  Ravi P. Srivastava ,  Mark A. Zaleski ,  Akshey Sehgal

IPC: H01L29/66 ,  H01L21/4763 ,  H01L21/311 ,  H01L21/768 ,  H01L23/532 ,  H01L23/528 ,  H01L23/522 ,  H01L21/02 ,  H01L21/3105 ,  H01L21/3213

CPC classification number: H01L23/528 ,  H01L21/02118 ,  H01L21/02126 ,  H01L21/31051 ,  H01L21/31138 ,  H01L21/31144 ,  H01L21/32133 ,  H01L21/76802 ,  H01L21/7681 ,  H01L21/76816 ,  H01L21/7682 ,  H01L21/76828 ,  H01L21/76832 ,  H01L21/76843 ,  H01L21/7685 ,  H01L21/76877 ,  H01L21/76879 ,  H01L21/76885 ,  H01L21/76892 ,  H01L23/5222 ,  H01L23/5226 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53266 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Embodiments of the present invention provide a semiconductor structure for BEOL (back end of line) integration. A directed self assembly (DSA) material is deposited and annealed to form two distinct phase regions. One of the phase regions is selectively removed, and the remaining phase region serves as a mask for forming cavities in an underlying layer of metal and/or dielectric. The process is then repeated to form complex structures with patterns of metal separated by dielectric regions.

公开(公告)号：US20160064514A1

公开(公告)日：2016-03-03

申请号：US14469014

申请日：2014-08-26

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Guillaume Bouche ,  Jason E. Stephens ,  Tuhin Guha Neogi ,  Mark A. Zaleski ,  Andy Chih-Hung Wei

IPC: H01L29/66 ,  H01L27/088 ,  H01L29/78

CPC classification number: H01L29/66545 ,  H01L21/76895 ,  H01L21/76897 ,  H01L21/823871 ,  H01L27/092 ,  H01L29/165 ,  H01L29/41783 ,  H01L29/6653

Abstract: An improved semiconductor structure and methods of fabrication that provide improved transistor contacts in a semiconductor structure are provided. A first block mask is formed over a portion of the semiconductor structure. This first block mask covers at least a portion of at least one source/drain (s/d) contact location. An s/d capping layer is formed over the s/d contact locations that are not covered by the first block mask. This s/d capping layer is comprised of a first capping substance. Then, a second block mask is formed over the semiconductor structure. This second block mask exposes at least one gate location. A gate capping layer, which comprises a second capping substance, is removed from the exposed gate location(s). Then a metal contact layer is deposited, which forms a contact to both the s/d contact location(s) and the gate contact location(s).

Abstract translation: 提供了一种在半导体结构中提供改进的晶体管触点的改进的半导体结构和制造方法。 在半导体结构的一部分上形成第一块掩模。 该第一块掩模覆盖至少一个源/漏（s / d）接触位置的至少一部分。 在未被第一块掩模覆盖的s / d接触位置上形成s / d覆盖层。 该s / d封盖层由第一封盖物质构成。 然后，在半导体结构上形成第二块掩模。 该第二块掩模暴露至少一个门位置。 包括第二封盖物质的栅极覆盖层从暴露的栅极位置移除。 然后沉积金属接触层，其形成与s / d接触位置和栅极接触位置的接触。

公开(公告)号：US20160049481A1

公开(公告)日：2016-02-18

申请号：US14926657

申请日：2015-10-29

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Andy Chih-Hung Wei ,  Guillaume Bouche ,  Mark A. Zaleski ,  Tuhin Guha Neogi ,  Jason E. Stephens ,  Jongwook Kye ,  Jia Zeng

IPC: H01L29/417 ,  H01L27/088 ,  H01L29/78

CPC classification number: H01L27/088 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/28568 ,  H01L21/76834 ,  H01L21/76895 ,  H01L21/76897 ,  H01L21/823475 ,  H01L21/823871 ,  H01L21/823878 ,  H01L23/528 ,  H01L23/53228 ,  H01L23/53257 ,  H01L23/5329 ,  H01L27/092 ,  H01L29/41725 ,  H01L29/41758 ,  H01L29/66462 ,  H01L29/78 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Embodiments of the present invention provide an improved semiconductor structure and methods of fabrication that provide transistor contacts that are self-aligned in two dimensions. Two different capping layers are used, each being comprised of a different material. The two capping layers are selectively etchable to each other. One capping layer is used for gate coverage while the other capping layer is used for source/drain coverage. Selective etch processes open the desired gates and source/drains, while block masks are used to cover elements that are not part of the connection scheme. A metallization line (layer) is deposited, making contact with the open elements to provide electrical connectivity between them.

Abstract translation: 本发明的实施例提供一种改进的半导体结构和制造方法，其提供在两维中自对准的晶体管接触。 使用两个不同的封盖层，每个覆盖层由不同的材料组成。 两个封盖层可以相互选择性地蚀刻。 一个覆盖层用于栅极覆盖，而另一个覆盖层用于源极/漏极覆盖。 选择性蚀刻工艺打开所需的栅极和源极/漏极，而块掩模用于覆盖不是连接方案一部分的元件。 沉积金属化线（层），与开放元件接触以提供它们之间的电连接。

公开(公告)号：US20150332959A1

公开(公告)日：2015-11-19

申请号：US14805443

申请日：2015-07-21

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Sunil K. Singh ,  Ravi P. Srivastava ,  Mark A. Zaleski ,  Akshey Sehgal

IPC: H01L21/768

CPC classification number: H01L23/528 ,  H01L21/02118 ,  H01L21/02126 ,  H01L21/31051 ,  H01L21/31138 ,  H01L21/31144 ,  H01L21/32133 ,  H01L21/76802 ,  H01L21/7681 ,  H01L21/76816 ,  H01L21/7682 ,  H01L21/76828 ,  H01L21/76832 ,  H01L21/76843 ,  H01L21/7685 ,  H01L21/76877 ,  H01L21/76879 ,  H01L21/76885 ,  H01L21/76892 ,  H01L23/5222 ,  H01L23/5226 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53266 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Embodiments of the present invention provide a semiconductor structure for BEOL (back end of line) integration. A directed self assembly (DSA) material is deposited and annealed to form two distinct phase regions. One of the phase regions is selectively removed, and the remaining phase region serves as a mask for forming cavities in an underlying layer of metal and/or dielectric. The process is then repeated to form complex structures with patterns of metal separated by dielectric regions.

Abstract translation: 本发明的实施例提供了一种用于BEOL（后端）集成的半导体结构。 定向自组装（DSA）材料被沉积并退火以形成两个不同的相位区域。 选择性地去除一个相区，并且剩余的相区用作在金属和/或电介质的下层中形成空腔的掩模。 然后重复该过程以形成具有由电介质区域分离的金属图案的复杂结构。

公开(公告)号：US20150287636A1

公开(公告)日：2015-10-08

申请号：US14246476

申请日：2014-04-07

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Andy Chih-Hung Wei ,  Guillaume Bouche ,  Mark A. Zaleski ,  Tuhin Guha Neogi ,  Jason E. Stephens ,  Jongwook Kye ,  Jia Zeng

IPC: H01L21/768 ,  H01L21/8234 ,  H01L27/092 ,  H01L21/02 ,  H01L21/285 ,  H01L21/8238 ,  H01L27/088 ,  H01L23/532

CPC classification number: H01L27/088 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/28568 ,  H01L21/76834 ,  H01L21/76895 ,  H01L21/76897 ,  H01L21/823475 ,  H01L21/823871 ,  H01L21/823878 ,  H01L23/528 ,  H01L23/53228 ,  H01L23/53257 ,  H01L23/5329 ,  H01L27/092 ,  H01L29/41725 ,  H01L29/41758 ,  H01L29/66462 ,  H01L29/78 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Embodiments of the present invention provide an improved semiconductor structure and methods of fabrication that provide transistor contacts that are self-aligned in two dimensions. Two different capping layers are used, each being comprised of a different material. The two capping layers are selectively etchable to each other. One capping layer is used for gate coverage while the other capping layer is used for source/drain coverage. Selective etch processes open the desired gates and source/drains, while block masks are used to cover elements that are not part of the connection scheme. A metallization line (layer) is deposited, making contact with the open elements to provide electrical connectivity between them.

Abstract translation: 本发明的实施例提供一种改进的半导体结构和制造方法，其提供在两维中自对准的晶体管接触。 使用两个不同的封盖层，每个覆盖层由不同的材料组成。 两个封盖层可以相互选择性地蚀刻。 一个覆盖层用于栅极覆盖，而另一个覆盖层用于源极/漏极覆盖。 选择性蚀刻工艺打开所需的栅极和源极/漏极，而块掩模用于覆盖不是连接方案一部分的元件。 沉积金属化线（层），与开放元件接触以提供它们之间的电连接。

公开(公告)号：US09117822B1

公开(公告)日：2015-08-25

申请号：US14264163

申请日：2014-04-29

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Sunil K. Singh ,  Ravi P. Srivastava ,  Mark A. Zaleski ,  Akshey Sehgal

IPC: H01L29/66 ,  H01L21/4763 ,  H01L21/31 ,  H01L23/532 ,  H01L23/528 ,  H01L23/522 ,  H01L21/768 ,  H01L21/02 ,  H01L21/311 ,  H01L21/3105 ,  H01L21/3213

CPC classification number: H01L23/528 ,  H01L21/02118 ,  H01L21/02126 ,  H01L21/31051 ,  H01L21/31138 ,  H01L21/31144 ,  H01L21/32133 ,  H01L21/76802 ,  H01L21/7681 ,  H01L21/76816 ,  H01L21/7682 ,  H01L21/76828 ,  H01L21/76832 ,  H01L21/76843 ,  H01L21/7685 ,  H01L21/76877 ,  H01L21/76879 ,  H01L21/76885 ,  H01L21/76892 ,  H01L23/5222 ,  H01L23/5226 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53266 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Embodiments of the present invention provide a semiconductor structure for BEOL (back end of line) integration. A directed self assembly (DSA) material is deposited and annealed to form two distinct phase regions. One of the phase regions is selectively removed, and the remaining phase region serves as a mask for forming cavities in an underlying layer of metal and/or dielectric. The process is then repeated to form complex structures with patterns of metal separated by dielectric regions.

Abstract translation: 本发明的实施例提供了一种用于BEOL（后端）集成的半导体结构。 定向自组装（DSA）材料被沉积并退火以形成两个不同的相位区域。 选择性地去除一个相区，并且剩余的相区用作在金属和/或电介质的下层中形成空腔的掩模。 然后重复该过程以形成具有由电介质区域分离的金属图案的复杂结构。

公开(公告)号：US20150236106A1

公开(公告)日：2015-08-20

申请号：US14184830

申请日：2014-02-20

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Mark A. Zaleski ,  Andy Chih-Hung Wei ,  Jason E. Stephens ,  Tuhin Guha Neogi ,  Guillaume Bouche

IPC: H01L29/417 ,  H01L29/78 ,  H01L27/088 ,  H01L29/66 ,  H01L29/51

CPC classification number: H01L29/41758 ,  H01L21/8234 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823871 ,  H01L27/088 ,  H01L27/0886 ,  H01L27/0924 ,  H01L29/165 ,  H01L29/41791 ,  H01L29/518 ,  H01L29/66348 ,  H01L29/66484 ,  H01L29/66545 ,  H01L29/66613 ,  H01L29/66621 ,  H01L29/66727 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785

Abstract: Embodiments of the present invention provide improved methods of contact formation. A self aligned contact scheme with reduced lithography requirements is disclosed. This reduces the risk of shorts between source/drains and gates, while providing improved circuit density. Cavities are formed adjacent to the gates, and a fill metal is deposited in the cavities to form contact strips. A patterning mask is then used to form smaller contacts by performing a partial metal recess of the contact strips.

Abstract translation: 本发明的实施例提供改进的接触形成方法。 公开了一种具有降低光刻要求的自对准接触方案。 这降低了源/漏极和栅极之间短路的风险，同时提供了改善的电路密度。 形成邻近门的腔，并且填充金属沉积在空腔中以形成接触条。 然后通过执行接触片的部分金属凹部来使用图案化掩模来形成更小的触点。