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    Shallow trench isolation structure with sigma cavity
    21.
    发明授权
    Shallow trench isolation structure with sigma cavity 有权
    浅沟槽隔离结构，带有Σ腔

    公开(公告)号：US09076868B1

    公开(公告)日：2015-07-07

    申请号：US14334953

    申请日：2014-07-18

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： HaoCheng Tsai ,  Min-hwa Chi

    IPC: H01L21/762 ,  H01L29/78 ,  H01L21/306 ,  H01L29/06 ,  H01L29/66

    CPC classification number: H01L29/0653 ,  H01L21/30608 ,  H01L21/3065 ,  H01L21/76224 ,  H01L21/76232 ,  H01L29/66568 ,  H01L29/66636 ,  H01L29/7846 ,  H01L29/7848

    Abstract: Embodiments of the present invention provide an improved shallow trench isolation structure and method of fabrication. The shallow trench isolation cavity includes an upper region having a sigma cavity shape, and a lower region having a substantially rectangular cross-section. The lower region is filled with a first material having good gap fill properties. The sigma cavity is filled with a second material having good stress-inducing properties. In some embodiments, source/drain stressor cavities may be eliminated, with the stress provided by the shallow trench isolation structure. In other embodiments, the stress from the shallow trench isolation structure may be used to complement or counteract stress from a source/drain stressor region of an adjacent transistor. This enables precise tuning of channel stress to achieve a desired carrier mobility for a transistor.

    Abstract translation: 本发明的实施例提供了一种改进的浅沟槽隔离结构和制造方法。 浅沟槽隔离腔包括具有西格玛腔形状的上部区域和具有基本矩形横截面的下部区域。 下部区域填充有具有良好间隙填充性能的第一材料。 西格玛腔填充有具有良好的应力诱导性能的第二材料。 在一些实施例中，可以消除源极/漏极应力源空穴，同时由浅沟槽隔离结构提供的应力。 在其他实施例中，来自浅沟槽隔离结构的应力可以用于补偿或抵消来自相邻晶体管的源极/漏极应力区域的应力。 这使得能够精确地调谐通道应力以实现晶体管的期望的载流子迁移率。

    Integrated circuits with programmable electrical connections and methods for fabricating the same
    22.
    发明授权
    Integrated circuits with programmable electrical connections and methods for fabricating the same 有权
    具有可编程电气连接的集成电路及其制造方法

    公开(公告)号：US09007803B2

    公开(公告)日：2015-04-14

    申请号：US13937962

    申请日：2013-07-09

    Applicant: GLOBALFOUNDRIES, Inc.

    Inventor： Yanxiang Liu ,  Min-hwa Chi

    IPC: G11C17/00 ,  H01L27/112 ,  H01L21/768 ,  G11C17/16

    CPC classification number: H01L27/11206 ,  G11C17/16 ,  H01L21/76816 ,  H01L23/5252 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: Methods and apparatus are provided for an integrated circuit with a programmable electrical connection. The apparatus includes an inactive area with a memory line passing over the inactive area. The memory line includes a programmable layer. An interlayer dielectric is positioned over the memory line and the inactive area, and an extending member extends through the interlayer dielectric. The extending member is electrically connected to the programmable layer of the memory line at a point above the inactive area.

    Abstract translation: 为具有可编程电气连接的集成电路提供了方法和装置。 该装置包括具有通过非活动区域的存储器线路的无效区域。 存储线包括可编程层。 层间电介质位于存储器线路和无源区域之上，并且延伸部件延伸穿过层间电介质。 延伸构件在非活动区域上方的点处电连接到存储器线路的可编程层。

    METHODS OF FORMING A FINFET SEMICONDUCTOR DEVICE BY PERFORMING AN EPITAXIAL GROWTH PROCESS
    23.
    发明申请
    METHODS OF FORMING A FINFET SEMICONDUCTOR DEVICE BY PERFORMING AN EPITAXIAL GROWTH PROCESS 有权
    通过执行外延生长过程形成FINFET半导体器件的方法

    公开(公告)号：US20140167120A1

    公开(公告)日：2014-06-19

    申请号：US13716686

    申请日：2012-12-17

    Applicant: GLOBALFOUNDRIES INC.

    Inventor： Min-hwa Chi ,  Nam Sung Kim

    IPC: H01L29/66 ,  H01L29/78

    CPC classification number: H01L27/0886 ,  H01L21/823821 ,  H01L21/845 ,  H01L29/66795 ,  H01L29/785

    Abstract: A method of forming a FinFET device involves performing an epitaxial growth process to form a layer of semiconducting material on a semiconducting substrate, wherein a first portion of the layer of semiconducting material will become a fin structure for the FinFET device and wherein a plurality of second portions of the layer of semiconducting material will become source/drain structures of the FinFET device, forming a gate insulation layer around at least a portion of the fin structure and forming a gate electrode above the gate insulation layer.

    Abstract translation: 形成FinFET器件的方法包括执行外延生长工艺以在半导体衬底上形成半导体材料层，其中半导体材料层的第一部分将成为FinFET器件的鳍结构，并且其中多个第二 半导体材料层的部分将成为FinFET器件的源极/漏极结构，在鳍状结构的至少一部分周围形成栅极绝缘层，并在栅极绝缘层的上方形成栅电极。

    COMBINATION FINFET AND PLANAR FET SEMICONDUCTOR DEVICE AND METHODS OF MAKING SUCH A DEVICE
    24.
    发明申请
    COMBINATION FINFET AND PLANAR FET SEMICONDUCTOR DEVICE AND METHODS OF MAKING SUCH A DEVICE 有权

    公开(公告)号：US20140151807A1

    公开(公告)日：2014-06-05

    申请号：US13705261

    申请日：2012-12-05

    Applicant: GLOBALFOUNDRIES INC.

    Inventor： Min-hwa Chi ,  Werner Juengling

    IPC: H01L21/84 ,  H01L27/12

    CPC classification number: H01L29/785 ,  H01L21/823431 ,  H01L21/845 ,  H01L27/0886 ,  H01L27/1211 ,  H01L29/7853

    Abstract: A device includes a plurality of trenches and fins defined in a substantially un-doped layer of semiconducting material, a gate insulation layer positioned on the fins and on the bottom of the trenches, a gate electrode and a device isolation structure. One method disclosed herein involves identifying a top width of each of a plurality of fins and a depth of a plurality of trenches to be formed in a substantially un-doped layer of semiconducting material, wherein, during operation, the device is adapted to operate in at least three distinguishable conditions depending upon a voltage applied to the device, performing at least one process operation to define the trenches and fins in the layer of semiconducting material, forming a gate insulation layer on the fins and on a bottom of the trenches and forming a gate electrode above the gate insulation layer.

    Fin removal method
    25.
    发明授权
    Fin removal method 有权
    翅片去除方法

    公开(公告)号：US08617996B1

    公开(公告)日：2013-12-31

    申请号：US13738435

    申请日：2013-01-10

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Min-hwa Chi ,  Honglian Shen ,  Changyong Xiao

    IPC: H01L21/311

    CPC classification number: H01L21/30604 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/823431 ,  H01L21/823821

    Abstract: Methods for removal of fins from a semiconductor structure are provided. A fin liner is applied to the fins. The fin liner is then removed from the fins that are to be removed. The fin liner is of a material that is selective compared to the semiconductor fins. Hence, the fins can be removed without significant damage to the fin liner. The subsets of fins that are to be removed are then removed, while the fin liner protects the adjacent fins that are to be kept.

    Abstract translation: 提供了从半导体结构中去除散热片的方法。 翅片衬垫应用于翅片。 然后将翅片衬垫从要去除的翅片上移除。 翅片衬套是与半导体翅片相比是选择性的材料。 因此，可以去除翅片而不会对翼片衬垫造成显着损坏。 然后去除要去除的翅片的子集，而翅片衬垫保护待保持的相邻翅片。

    Method of forming gate-all-around (GAA) FinFET and GAA FinFET formed thereby
    26.
    发明授权
    Method of forming gate-all-around (GAA) FinFET and GAA FinFET formed thereby 有权

    公开(公告)号：US10475899B2

    公开(公告)日：2019-11-12

    申请号：US16190549

    申请日：2018-11-14

    Applicant: GLOBALFOUNDRIES INC.

    Inventor： Ruilong Xie ,  Andreas Knorr ,  Julien Frougier ,  Hui Zang ,  Min-hwa Chi

    IPC: H01L29/423 ,  H01L29/66 ,  H01L29/06 ,  H01L29/49 ,  H01L29/786 ,  H01L27/088

    Abstract: A method of forming a GAA FinFET, including: forming a fin on a substrate, the substrate having a STI layer formed thereon and around a portion of a FIN-bottom portion of the fin, the fin having a dummy gate formed thereover, the dummy gate having a gate sidewall spacer on sidewalls thereof; forming a FIN-void and an under-FIN cavity in the STI layer; forming first spacers by filling the under-FIN cavity and FIN-void with a first fill; removing the dummy gate, thereby exposing both FIN-bottom and FIN-top portions of the fin underneath the gate; creating an open area underneath the exposed FIN-top by removing the exposed FIN-bottom; and forming a second spacer by filling the open area with a second fill; wherein a distance separates a top-most surface of the second spacer from a bottom-most surface of the FIN-top portion. A GAA FinFET formed by the method is also disclosed.

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