公开(公告)号：US20180033701A1

公开(公告)日：2018-02-01

申请号：US15728445

申请日：2017-10-09

Applicant: GLOBALFOUNDRIES INC.

Inventor： Guillaume Bouche ,  Tuhin Guha Neogi ,  Andy Chi-Hung Wei ,  Jia Zeng ,  Jongwook Kye ,  Jason Eugene Stephens ,  Irene Yuh-Ling Lin ,  Sudharshanan Raghunathan ,  Lei Yuan

IPC: H01L21/8238 ,  H01L23/535 ,  H01L21/027 ,  G06F17/50 ,  H01L21/768 ,  H01L21/285 ,  H01L27/092 ,  H01L21/8234

Abstract: At least one method, apparatus and system disclosed herein for forming a finFET device having a pass-through structure. A first gate structure and a second gate structure are formed on a semiconductor wafer. A first active area is formed on one end of the first and second gate structures. A second active area is formed on the other end of the first and second gate structures. A trench silicide (TS) structure self-aligned to the first and second gate structures is formed. The TS structure is configured to operatively couple the first active area to the second active area.

公开(公告)号：US09818651B2

公开(公告)日：2017-11-14

申请号：US15067953

申请日：2016-03-11

Applicant: GLOBALFOUNDRIES INC.

Inventor： Guillaume Bouche ,  Tuhin Guha Neogi ,  Andy Chi-Hung Wei ,  Jia Zeng ,  Jongwook Kye ,  Jason Eugene Stephens ,  Irene Yuh-Ling Lin ,  Sudharshanan Raghunathan ,  Lei Yuan

IPC: H01L21/00 ,  H01L21/8238 ,  H01L21/8234 ,  H01L21/768 ,  H01L21/285 ,  H01L21/027 ,  H01L27/092 ,  H01L23/535 ,  G06F17/50

CPC classification number: H01L21/823871 ,  G06F17/5072 ,  H01L21/027 ,  H01L21/28518 ,  H01L21/76897 ,  H01L21/823431 ,  H01L21/823475 ,  H01L21/823821 ,  H01L23/535 ,  H01L27/0886 ,  H01L27/0924

Abstract: At least one method, apparatus and system disclosed herein for forming a finFET device having a pass-through structure. A first gate structure and a second gate structure are formed on a semiconductor wafer. A first active area is formed on one end of the first and second gate structures. A second active area is formed on the other end of the first and second gate structures. A trench silicide (TS) structure self-aligned to the first and second gate structures is formed. The TS structure is configured to operatively couple the first active area to the second active area.

公开(公告)号：US20170221886A1

公开(公告)日：2017-08-03

申请号：US15490702

申请日：2017-04-18

Applicant: GLOBALFOUNDRIES INC.

Inventor： Andy Chih-Hung Wei ,  Guillaume Bouche ,  Mark A. Zaleski ,  Tuhin Guha Neogi ,  Jason E. Stephens ,  Jongwook Kye ,  Jia Zeng

IPC: H01L27/088 ,  H01L21/8238 ,  H01L27/092 ,  H01L21/8234 ,  H01L23/528 ,  H01L23/532

CPC classification number: H01L27/088 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/28568 ,  H01L21/76834 ,  H01L21/76895 ,  H01L21/76897 ,  H01L21/823475 ,  H01L21/823871 ,  H01L21/823878 ,  H01L23/528 ,  H01L23/53228 ,  H01L23/53257 ,  H01L23/5329 ,  H01L27/092 ,  H01L29/41725 ,  H01L29/41758 ,  H01L29/66462 ,  H01L29/78 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Embodiments of the present invention provide an improved semiconductor structure and methods of fabrication that provide transistor contacts that are self-aligned in two dimensions. Two different capping layers are used, each being comprised of a different material. The two capping layers are selectively etchable to each other. One capping layer is used for gate coverage while the other capping layer is used for source/drain coverage. Selective etch processes open the desired gates and source/drains, while block masks are used to cover elements that are not part of the connection scheme. A metallization line (layer) is deposited, making contact with the open elements to provide electrical connectivity between them.

公开(公告)号：US09666488B1

公开(公告)日：2017-05-30

申请号：US15095612

申请日：2016-04-11

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Tuhin Guha Neogi ,  David Pritchard ,  Scott Luning ,  Guillaume Bouche ,  David Doman

IPC: H01L21/00 ,  H01L27/00 ,  H01L29/00 ,  H01L21/8238 ,  H01L21/84 ,  H01L21/285 ,  H01L27/092 ,  H01L27/12 ,  H01L29/08 ,  H01L29/161 ,  H01L29/165 ,  H01L29/78

CPC classification number: H01L21/823814 ,  H01L21/28518 ,  H01L21/823807 ,  H01L21/823864 ,  H01L21/823871 ,  H01L21/84 ,  H01L27/092 ,  H01L27/1203 ,  H01L29/0847 ,  H01L29/161 ,  H01L29/165 ,  H01L29/7838 ,  H01L29/7848

Abstract: A method of forming a silicide layer as a pass-through contact under a gate contact between p-epilayer and n-epilayer source/drains and the resulting device are provided. Embodiments include depositing a semiconductor layer over a substrate; forming a pFET gate on a p-side of the semiconductor layer and a nFET gate on a n-side of the semiconductor layer; forming a gate contact between the pFET gate and the nFET gate; forming raised source/drains on opposite sides of each of the pFET and nFET gates; and forming a metal silicide over a first raised source/drain on the p-side and over a second raised source/drain on the n-side, wherein the metal silicide extends from the first raised source/drain to the second raised source/drain and below the gate contact between the pFET and nFET gates.

公开(公告)号：US20160064514A1

公开(公告)日：2016-03-03

申请号：US14469014

申请日：2014-08-26

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Guillaume Bouche ,  Jason E. Stephens ,  Tuhin Guha Neogi ,  Mark A. Zaleski ,  Andy Chih-Hung Wei

IPC: H01L29/66 ,  H01L27/088 ,  H01L29/78

CPC classification number: H01L29/66545 ,  H01L21/76895 ,  H01L21/76897 ,  H01L21/823871 ,  H01L27/092 ,  H01L29/165 ,  H01L29/41783 ,  H01L29/6653

Abstract: An improved semiconductor structure and methods of fabrication that provide improved transistor contacts in a semiconductor structure are provided. A first block mask is formed over a portion of the semiconductor structure. This first block mask covers at least a portion of at least one source/drain (s/d) contact location. An s/d capping layer is formed over the s/d contact locations that are not covered by the first block mask. This s/d capping layer is comprised of a first capping substance. Then, a second block mask is formed over the semiconductor structure. This second block mask exposes at least one gate location. A gate capping layer, which comprises a second capping substance, is removed from the exposed gate location(s). Then a metal contact layer is deposited, which forms a contact to both the s/d contact location(s) and the gate contact location(s).

Abstract translation: 提供了一种在半导体结构中提供改进的晶体管触点的改进的半导体结构和制造方法。 在半导体结构的一部分上形成第一块掩模。 该第一块掩模覆盖至少一个源/漏（s / d）接触位置的至少一部分。 在未被第一块掩模覆盖的s / d接触位置上形成s / d覆盖层。 该s / d封盖层由第一封盖物质构成。 然后，在半导体结构上形成第二块掩模。 该第二块掩模暴露至少一个门位置。 包括第二封盖物质的栅极覆盖层从暴露的栅极位置移除。 然后沉积金属接触层，其形成与s / d接触位置和栅极接触位置的接触。

公开(公告)号：US20160049481A1

公开(公告)日：2016-02-18

申请号：US14926657

申请日：2015-10-29

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Andy Chih-Hung Wei ,  Guillaume Bouche ,  Mark A. Zaleski ,  Tuhin Guha Neogi ,  Jason E. Stephens ,  Jongwook Kye ,  Jia Zeng

IPC: H01L29/417 ,  H01L27/088 ,  H01L29/78

CPC classification number: H01L27/088 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/28568 ,  H01L21/76834 ,  H01L21/76895 ,  H01L21/76897 ,  H01L21/823475 ,  H01L21/823871 ,  H01L21/823878 ,  H01L23/528 ,  H01L23/53228 ,  H01L23/53257 ,  H01L23/5329 ,  H01L27/092 ,  H01L29/41725 ,  H01L29/41758 ,  H01L29/66462 ,  H01L29/78 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Embodiments of the present invention provide an improved semiconductor structure and methods of fabrication that provide transistor contacts that are self-aligned in two dimensions. Two different capping layers are used, each being comprised of a different material. The two capping layers are selectively etchable to each other. One capping layer is used for gate coverage while the other capping layer is used for source/drain coverage. Selective etch processes open the desired gates and source/drains, while block masks are used to cover elements that are not part of the connection scheme. A metallization line (layer) is deposited, making contact with the open elements to provide electrical connectivity between them.

Abstract translation: 本发明的实施例提供一种改进的半导体结构和制造方法，其提供在两维中自对准的晶体管接触。 使用两个不同的封盖层，每个覆盖层由不同的材料组成。 两个封盖层可以相互选择性地蚀刻。 一个覆盖层用于栅极覆盖，而另一个覆盖层用于源极/漏极覆盖。 选择性蚀刻工艺打开所需的栅极和源极/漏极，而块掩模用于覆盖不是连接方案一部分的元件。 沉积金属化线（层），与开放元件接触以提供它们之间的电连接。

公开(公告)号：US20150287636A1

公开(公告)日：2015-10-08

申请号：US14246476

申请日：2014-04-07

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Andy Chih-Hung Wei ,  Guillaume Bouche ,  Mark A. Zaleski ,  Tuhin Guha Neogi ,  Jason E. Stephens ,  Jongwook Kye ,  Jia Zeng

IPC: H01L21/768 ,  H01L21/8234 ,  H01L27/092 ,  H01L21/02 ,  H01L21/285 ,  H01L21/8238 ,  H01L27/088 ,  H01L23/532

CPC classification number: H01L27/088 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/28568 ,  H01L21/76834 ,  H01L21/76895 ,  H01L21/76897 ,  H01L21/823475 ,  H01L21/823871 ,  H01L21/823878 ,  H01L23/528 ,  H01L23/53228 ,  H01L23/53257 ,  H01L23/5329 ,  H01L27/092 ,  H01L29/41725 ,  H01L29/41758 ,  H01L29/66462 ,  H01L29/78 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Embodiments of the present invention provide an improved semiconductor structure and methods of fabrication that provide transistor contacts that are self-aligned in two dimensions. Two different capping layers are used, each being comprised of a different material. The two capping layers are selectively etchable to each other. One capping layer is used for gate coverage while the other capping layer is used for source/drain coverage. Selective etch processes open the desired gates and source/drains, while block masks are used to cover elements that are not part of the connection scheme. A metallization line (layer) is deposited, making contact with the open elements to provide electrical connectivity between them.

Abstract translation: 本发明的实施例提供一种改进的半导体结构和制造方法，其提供在两维中自对准的晶体管接触。 使用两个不同的封盖层，每个覆盖层由不同的材料组成。 两个封盖层可以相互选择性地蚀刻。 一个覆盖层用于栅极覆盖，而另一个覆盖层用于源极/漏极覆盖。 选择性蚀刻工艺打开所需的栅极和源极/漏极，而块掩模用于覆盖不是连接方案一部分的元件。 沉积金属化线（层），与开放元件接触以提供它们之间的电连接。

公开(公告)号：US20150236106A1

公开(公告)日：2015-08-20

申请号：US14184830

申请日：2014-02-20

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Mark A. Zaleski ,  Andy Chih-Hung Wei ,  Jason E. Stephens ,  Tuhin Guha Neogi ,  Guillaume Bouche

IPC: H01L29/417 ,  H01L29/78 ,  H01L27/088 ,  H01L29/66 ,  H01L29/51

CPC classification number: H01L29/41758 ,  H01L21/8234 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823871 ,  H01L27/088 ,  H01L27/0886 ,  H01L27/0924 ,  H01L29/165 ,  H01L29/41791 ,  H01L29/518 ,  H01L29/66348 ,  H01L29/66484 ,  H01L29/66545 ,  H01L29/66613 ,  H01L29/66621 ,  H01L29/66727 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785

Abstract: Embodiments of the present invention provide improved methods of contact formation. A self aligned contact scheme with reduced lithography requirements is disclosed. This reduces the risk of shorts between source/drains and gates, while providing improved circuit density. Cavities are formed adjacent to the gates, and a fill metal is deposited in the cavities to form contact strips. A patterning mask is then used to form smaller contacts by performing a partial metal recess of the contact strips.

Abstract translation: 本发明的实施例提供改进的接触形成方法。 公开了一种具有降低光刻要求的自对准接触方案。 这降低了源/漏极和栅极之间短路的风险，同时提供了改善的电路密度。 形成邻近门的腔，并且填充金属沉积在空腔中以形成接触条。 然后通过执行接触片的部分金属凹部来使用图案化掩模来形成更小的触点。

公开(公告)号：US08962485B2

公开(公告)日：2015-02-24

申请号：US13897890

申请日：2013-05-20

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Mohamed Salama ,  Tuhin Guha Neogi ,  Scott Beasor

IPC: H01L21/311 ,  H01L21/283

CPC classification number: H01L21/76816 ,  H01L21/28518 ,  H01L27/0207

Abstract: A method of silicide formation in a semiconductor fabrication process is disclosed. An active area (RX) mask is used to form an active silicon area, and is then reused to form a trench transfer (TT) area. A trench block (TB) mask is logically ANDed with the active area (RX) mask to form a trench silicide (TS) region.

Abstract translation: 公开了半导体制造工艺中硅化物形成的方法。 使用有源区（RX）掩模形成活性硅区，然后再利用以形成沟槽转移（TT）区。 沟槽块（TB）掩模与有源区（RX）掩模进行逻辑“与”，以形成沟槽硅化物（TS）区域。

公开(公告)号：US20140342556A1

公开(公告)日：2014-11-20

申请号：US13897890

申请日：2013-05-20

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Mohamed Salama ,  Tuhin Guha Neogi ,  Scott Beasor

IPC: H01L21/283

CPC classification number: H01L21/76816 ,  H01L21/28518 ,  H01L27/0207

Abstract: A method of silicide formation in a semiconductor fabrication process is disclosed. An active area (RX) mask is used to form an active silicon area, and is then reused to form a trench transfer (TT) area. A trench block (TB) mask is logically ANDed with the active area (RX) mask to form a trench silicide (TS) region.

Abstract translation: 公开了半导体制造工艺中硅化物形成的方法。 使用有源区（RX）掩模形成活性硅区，然后再利用以形成沟槽转移（TT）区。 沟槽块（TB）掩模与有源区（RX）掩模进行逻辑“与”，以形成沟槽硅化物（TS）区域。