公开(公告)号：US09812336B2

公开(公告)日：2017-11-07

申请号：US14519215

申请日：2014-10-21

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Michael Ganz ,  Bingwu Liu ,  Johannes Marinus Van Meer ,  Sruthi Muralidharan

IPC: H01L21/02 ,  H01L21/266 ,  H01L29/78 ,  H01L21/324 ,  H01L29/66 ,  H01L21/265 ,  H01L21/3213 ,  H01L21/268

CPC classification number: H01L21/324 ,  H01L21/0217 ,  H01L21/0228 ,  H01L21/265 ,  H01L21/266 ,  H01L21/268 ,  H01L21/31055 ,  H01L21/32139 ,  H01L29/66795 ,  H01L29/66803 ,  H01L29/7851 ,  H01L29/7854

Abstract: The invention provides a method of forming a semiconductor structure, which include: providing an intermediate semiconductor structure having semiconductor substrate, a fin having an EG oxide layer in contact with at least a portion of the fin, and a gate stack disposed over a portion of the fin; forming a silicon nitride layer over portions of the fin that are not located under the gate stack; and after forming the silicon nitride layer, performing one or more ion implantation steps on the intermediate semiconductor structure. The invention also provides a method of forming a semiconductor structure including: providing an intermediate semiconductor structure having a semiconductor substrate, a fin having an EG oxide layer in contact with at least a portion of the fin, and a gate material disposed over the fin; forming, over the fin and gate material of the intermediate semiconductor structure, a gate stack hardmask including an oxide layer; forming a silicon nitride barrier layer on the oxide layer of the gate stack hardmask; performing one or more gate stack hardmask patterning steps; removing the EG oxide layer from portions of the fin that are not located under the gate; and subsequent to removing the EG oxide layer from portions of the fin that are not located under the gate, performing one or more ion implantation steps.

公开(公告)号：US09761594B2

公开(公告)日：2017-09-12

申请号：US14043871

申请日：2013-10-02

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Xusheng Wu ,  Bingwu Liu ,  Randy Mann

IPC: H01L27/11 ,  H01L21/265 ,  H01L27/088 ,  H01L21/8234 ,  H01L29/66 ,  H01L27/02 ,  H01L21/266 ,  H01L29/78

CPC classification number: H01L27/1104 ,  H01L21/26586 ,  H01L21/266 ,  H01L21/823431 ,  H01L27/0207 ,  H01L27/0886 ,  H01L29/66803 ,  H01L29/785

Abstract: Approaches for providing a hardmask used during a halo/extension implant of a static random access memory (SRAM) layout for a semiconductor device are disclosed. Specifically, approaches are provided for forming a pull-down (PD) transistor over a substrate; forming a pass-gate (PG) transistor over the substrate; and patterning a hardmask over the device, the hardmask including a first section adjacent the PD transistor and a second section adjacent the PG transistor, wherein a distance between the first section and the PD transistor is shorter than a distance between the second section and the PG transistor. The respective distances between the first section and the PD transistor, and the second section and the PG transistor, are selected to prevent a halo/extension implant from impacting one side of the PD transistor, while allowing the halo/extension implant to impact both sides of the PG transistor.

公开(公告)号：US09691787B2

公开(公告)日：2017-06-27

申请号：US14878332

申请日：2015-10-08

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hui Zang ,  Bingwu Liu

IPC: H01L27/12 ,  H01L21/84 ,  H01L21/8234

CPC classification number: H01L27/1207 ,  H01L21/8234 ,  H01L21/84

Abstract: Bulk semiconductor devices are co-fabricated on a bulk semiconductor substrate with SOI devices. The SOI initially covers the entire substrate and is then removed from the bulk device region. The bulk device region has a thicker dielectric on the substrate than the SOI region. The regions are separated by isolation material, and may or may not be co-planar.

公开(公告)号：US09496280B1

公开(公告)日：2016-11-15

申请号：US14700748

申请日：2015-04-30

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hui Zang ,  Bingwu Liu ,  Xusheng Wu

IPC: H01L21/76 ,  H01L27/12 ,  H01L21/84 ,  H01L29/66 ,  H01L21/02 ,  H01L29/78 ,  H01L29/73 ,  H01L29/08 ,  H01L29/06

CPC classification number: H01L29/0684 ,  H01L21/8249 ,  H01L21/84 ,  H01L27/0623 ,  H01L27/1207 ,  H01L29/0847 ,  H01L29/66242 ,  H01L29/66272 ,  H01L29/66568 ,  H01L29/732 ,  H01L29/7371 ,  H01L29/78

Abstract: A method can include epitaxially growing epitaxial growth material within a logic region of a semiconductor structure. A method can include performing simultaneously with the growing epitaxial growth within an analog region of the semiconductor structure. A method can include performing epitaxial growth to form an epitaxial growth formation that defines an electrode of an analog device within an analog region of the semiconductor structure, wherein the performing includes using a first surface and a second surface as seed surfaces.

Abstract translation: 一种方法可以包括在半导体结构的逻辑区域内外延生长外延生长材料。 一种方法可以包括与半导体结构的模拟区域内的增长的外延生长同时执行。 一种方法可以包括进行外延生长以形成限定半导体结构的模拟区域内的模拟器件的电极的外延生长结构，其中执行包括使用第一表面和第二表面作为晶种表面。

公开(公告)号：US09431396B2

公开(公告)日：2016-08-30

申请号：US14609564

申请日：2015-01-30

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hui Zang ,  Bingwu Liu

IPC: H01L21/76 ,  H01L29/78 ,  H01L27/088 ,  H01L29/10 ,  H01L21/8234 ,  H01L21/762 ,  H01L21/3213 ,  H01L21/02 ,  H01L27/02 ,  H01L21/28 ,  H01L29/66 ,  H01L29/417

CPC classification number: H01L27/0886 ,  H01L21/0217 ,  H01L21/28035 ,  H01L21/32139 ,  H01L21/76224 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823475 ,  H01L27/0207 ,  H01L29/1083 ,  H01L29/41758 ,  H01L29/66545

Abstract: Methods of forming a SDB with a partial or complete insulator structure formed over the SDB and resulting devices are provided. Embodiments include forming a SDB with a first width in a substrate; forming a first metal gate in an ILD on top of the SDB, with a second width larger than the first width; forming second and third metal gates in the ILD on the substrate on opposite sides of the first metal gate, the second and third metal gates laterally separated from the first metal gate; forming a photoresist over the second and third gates; removing the first metal gate down to the SDB, forming a cavity; removing the photoresist; and filling the cavity with an insulator layer.

Abstract translation: 提供了形成在SDB上形成的部分或完全绝缘体结构的SDB和所得到的器件的方法。 实施例包括在衬底中形成具有第一宽度的SDB; 在所述SDB顶部的ILD中形成第一金属栅极，第二宽度大于所述第一宽度; 在第一金属栅极的相对侧上的衬底上的ILD中形成第二和第三金属栅极，第二和第三金属栅极与第一金属栅极横向分离; 在第二和第三栅极上形成光致抗蚀剂; 将第一金属栅极移到SDB上，形成空腔; 去除光致抗蚀剂; 并用绝缘体层填充空腔。

公开(公告)号：US20150364595A1

公开(公告)日：2015-12-17

申请号：US14731876

申请日：2015-06-05

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Bingwu Liu ,  Hui Zang

IPC: H01L29/78 ,  H01L29/66

CPC classification number: H01L29/785 ,  H01L21/823431 ,  H01L21/845 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/6681 ,  H01L29/66818

Abstract: One illustrative method disclosed herein includes, among other things, forming a fin protection layer around a fin, forming a sacrificial gate electrode above a section of the fin protection layer, forming at least one sidewall spacer adjacent the sacrificial gate electrode, removing the sacrificial gate electrode to define a gate cavity that exposes a portion of the fin protection layer, oxidizing at least the exposed portion of the fin protection layer to thereby form an oxidized portion of the fin protection layer, and removing the oxidized portion of the fin protection layer so as to thereby expose a surface of the fin within the gate cavity.

Abstract translation: 本文公开的一种说明性方法包括在鳍周围形成翅片保护层，在翅片保护层的一部分上形成牺牲栅电极，形成邻近牺牲栅电极的至少一个侧壁间隔物，去除牺牲栅极 电极，以限定露出所述鳍片保护层的一部分的栅极腔，至少氧化所述鳍片保护层的暴露部分，从而形成所述鳍片保护层的氧化部分，以及去除所述鳍片保护层的氧化部分，从而 从而使得在门腔内的翅片的表面露出。

公开(公告)号：US20140273389A1

公开(公告)日：2014-09-18

申请号：US13799814

申请日：2013-03-13

Applicant: Globalfoundries Inc.

Inventor： Bingwu Liu ,  Baofu Zhu ,  Nam Sung Kim

IPC: H01L29/66

CPC classification number: H01L29/66545 ,  H01L21/28123 ,  H01L29/165 ,  H01L29/49 ,  H01L29/66575 ,  H01L29/66636 ,  H01L29/78

Abstract: An approach for controlling a critical dimension (CD) of a RMG of a semiconductor device is provided. Specifically, embodiments of the present invention allow for CD consistency between a dummy gate and a subsequent RMG. In a typical embodiment, a dummy gate having a cap layer is formed over a substrate. A re-oxide layer is then formed over the substrate and around the dummy gate. A set of doping implants will then be implanted in the substrate, and the re-oxide layer will subsequently be removed (after the set of doping implants have been implanted). A set of spacers will then be formed along a set of side walls of the dummy gate and an epitaxial layer will be formed around the set of side walls. Thereafter, the dummy gate will be replaced with a metal gate (e.g., an aluminum or tungsten body having a high-k metal liner there-around).

Abstract translation: 提供了一种用于控制半导体器件的RMG的临界尺寸（CD）的方法。 具体地，本发明的实施例允许伪门和随后的RMG之间的CD一致性。 在典型的实施例中，在衬底上形成具有盖层的虚拟栅极。 然后在衬底上并围绕虚拟栅极形成再氧化物层。 然后将一组掺杂植入物植入衬底中，并且随后将去除再氧化物层（在植入了该组掺杂植入物之后）。 然后将沿着伪栅极的一组侧壁形成一组间隔物，并且将在该组侧壁周围形成外延层。 此后，虚拟栅极将被金属栅极（例如，具有高k金属衬垫的铝或钨体）替代。

公开(公告)号：US20200066883A1

公开(公告)日：2020-02-27

申请号：US16108152

申请日：2018-08-22

Applicant: GLOBALFOUNDRIES INC.

Inventor： Yanping Shen ,  Hui Zang ,  Bingwu Liu ,  Manoj Joshi ,  Jae Gon Lee ,  Hsien-Ching Lo ,  Zhaoying Hu

IPC: H01L29/66 ,  H01L21/308 ,  H01L29/78 ,  H01L29/08 ,  H01L21/8234

Abstract: Methods form devices by patterning a lower layer to form a fin, and forming a sacrificial gate along sidewalls of the fin. Such methods form a mask with cut openings on the sacrificial gate and remove sections of the fin and the sacrificial gate exposed through the cut openings to divide the fin into fin portions and create cut areas between the fin portions. Additionally, these methods remove the mask, epitaxially grow source/drains in the cut areas, replace the sacrificial gate with a gate conductor, and form a gate contact on the gate conductor over a center of the fin portions.

公开(公告)号：US10483377B2

公开(公告)日：2019-11-19

申请号：US15821091

申请日：2017-11-22

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hui Zang ,  Bingwu Liu

IPC: H01L29/66 ,  H01L29/78

Abstract: Devices and methods of growing unmerged epitaxy for fin field-effect transistor (FinFet) devices are provided. One method includes, for instance: obtaining a wafer having at least one source, at least one drain, and at least one fin; etching to expose at least a portion of the at least one fin; forming at least one sacrificial gate structure; and forming a first layer of an epitaxial growth on the at least one fin. One device includes, for instance: a wafer having at least one source, at least one drain, and at least one fin; a first layer of an epitaxial growth on the at least one fin; at least one second layer of an epitaxial growth superimposing the first layer of an epitaxial growth; and a first contact region over the at least one source and a second contact region over the at least one drain.

公开(公告)号：US20190006350A1

公开(公告)日：2019-01-03

申请号：US15638850

申请日：2017-06-30

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Bingwu Liu ,  Hui Zang

IPC: H01L27/06 ,  H01L21/8234

Abstract: Structures for a passive device of an integrated circuits and associated fabrication methods. A semiconductor substrate having raised fins and an dielectric isolation layer between the fins is formed. An etch stop layer is formed over the dielectric isolation layer between fins of a passive device. An interlayer dielectric layer is formed over the fins and etch stop layer. The interlayer dielectric layer is selectively etched to form an opening for conductive contact to the fins, where the etch stop layer prevents etching of the dielectric isolation layer. A conductive contact is formed to contact the plurality of fins, with the conductive contact terminating at the etch stop layer.