公开(公告)号：US20140124894A1

公开(公告)日：2014-05-08

申请号：US14066545

申请日：2013-10-29

Applicant: IMEC

Inventor： Geert Hellings ,  Mirko Scholz ,  Dimitri Linten

IPC: H01L23/60 ,  H01L29/66 ,  H01L29/73

CPC classification number: H01L23/60 ,  H01L27/0255 ,  H01L29/0649 ,  H01L29/0688 ,  H01L29/36 ,  H01L29/6609 ,  H01L29/66098 ,  H01L29/66106 ,  H01L29/66234 ,  H01L29/7302 ,  H01L29/735 ,  H01L29/866 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The disclosed technology relates to a semiconductor device comprising a diode junction between two semiconductor regions of different doping types. In one aspect, the diode comprises a junction formed between an upper portion of an active area and a remainder of the active area, where the active area is defined in a substrate between two field dielectric regions. The upper portion is a portion of the active area that has a width smaller than a width of the active area itself. In another aspect, the semiconductor device is an electrostatic discharge protection device (ESD) comprising such a diode. In addition, the active area has a doping profile that exhibits a maximum value at the surface of the active area, and changes to a minimum value at a first depth, where the first depth can be greater in value than half of a depth of the upper portion. In another aspect, a method of fabrication the device does not require a separate ESD implant for lowering the holding voltage and can allow for a reduction in the number of processing steps as well as other devices comprising a diode junction.

Abstract translation: 所公开的技术涉及包括不同掺杂类型的两个半导体区域之间的二极管结的半导体器件。 在一个方面，二极管包括在有源区的上部和有源区的其余部分之间形成的结，其中有源区限定在两个场介电区之间的衬底中。 上部是活动区域的宽度小于有效区域本身的宽度的部分。 在另一方面，半导体器件是包括这种二极管的静电放电保护器件（ESD）。 此外，有源区具有在有源区的表面处呈现最大值的掺杂分布，并且在第一深度处变化为最小值，其中第一深度可以比值的深度的一半更大 上部。 在另一方面，制造该器件的方法不需要用于降低保持电压的单独的ESD注入，并且可以允许减少处理步骤的数量以及包括二极管结的其它器件。

公开(公告)号：US20240429274A1

公开(公告)日：2024-12-26

申请号：US18753824

申请日：2024-06-25

Applicant: IMEC VZW

Inventor： Geert Hellings ,  Pieter Schuddinck

IPC: H01L29/06 ,  H01L27/092 ,  H01L29/417 ,  H01L29/423 ,  H01L29/775 ,  H01L29/786

Abstract: Provided herein is a nanosheet device that includes a first and a second transistor structure, each comprising a respective source region, drain region, and channel region extending between the respective source and drain regions, a dielectric wall, a gate structure, and a gate spacer, wherein the channel region of the first transistor structure includes a first set of vertically stacked channel layers, wherein each channel layer of the first set of vertically stacked channel layers has an inward facing surface contacting a first side surface of the dielectric wall, and wherein the channel region of the second transistor structure includes a second set of vertically stacked channel layers, and wherein each channel layer of the second set of vertically stacked channel layers has an inward facing surface contacting a second side surface, opposite to the first side surface, of the dielectric wall

公开(公告)号：US11735645B2

公开(公告)日：2023-08-22

申请号：US17099339

申请日：2020-11-16

Applicant: IMEC VZW ,  Katholieke Universiteit Leuven, KU LEUVEN R & D

Inventor： Koen Martens ,  Sybren Santermans ,  Geert Hellings ,  David Barge

IPC: H01L29/66 ,  G01N27/414

CPC classification number: H01L29/6656 ,  G01N27/4145

Abstract: A method for forming a sensor is provided. The method includes: providing an active region comprising a channel having: a length, and a periphery consisting of one or more surfaces having said length, said periphery comprising a first part and a second part, each part having said length, the first part representing from 10 to 75% of the area of the periphery and the second part representing from 25 to 90% of the area of the periphery; providing a first dielectric structure on the entire first part, the first dielectric structure having a maximal equivalent oxide thickness; and providing a second dielectric structure on the entire second part, the second dielectric structure having a minimal equivalent oxide thickness larger than the maximal equivalent oxide thickness of the first dielectric structure.

公开(公告)号：US11114435B2

公开(公告)日：2021-09-07

申请号：US15382376

申请日：2016-12-16

Applicant: IMEC VZW ,  Katholieke Universiteit Leuven

Inventor： Geert Hellings ,  Roman Boschke ,  Dimitri Linten ,  Naoto Horiguchi

IPC: H01L27/088 ,  H01L29/78 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/417 ,  H01L29/66

Abstract: The disclosed technology generally relates to semiconductor devices, and more particularly to FinFET transistors. In one aspect, at least three fins are arranged to extend in parallel in a first direction and are laterally separated from each other in a second direction by shallow trench isolation structures having a first fin spacing, where at least a portion of each fin protrudes out from a substrate. At least a portion of each of a first fin and a second fin of the at least three fins vertically protrude to a level higher than an upper surface of the shallow trench isolation structures. A third fin is formed laterally between the first fin and the second fin in the second direction, where the third fin has a non-protruding region which extends vertically to a level below or equal to the upper surface of the shallow trench isolation structures.

公开(公告)号：US10680098B2

公开(公告)日：2020-06-09

申请号：US15389217

申请日：2016-12-22

Applicant: IMEC VZW

Inventor： Shih-Hung Chen ,  Dimitri Linten ,  Geert Hellings

IPC: H01L29/78 ,  H01L29/417 ,  H01L29/10 ,  H01L29/06 ,  H01L29/08

Abstract: An LDMOS device in FinFET technology is disclosed. In one aspect, the device includes a first region substantially surrounded by a second region of different polarity. The device further includes a first fin in the first region, extending into the second region, the first fin including a doped source region connected with a first local interconnect. The device further includes a second fin in the second region, including a doped drain region connected with a second local interconnect. The device further includes a third fin parallel with the first and second fins including a doped drain region connected with the second local interconnect. The device further includes a gate over the first fin at the border between the first and second regions. A first current path runs over the first and second fins. A second current path runs over and perpendicular to the first fin towards the third fin.

公开(公告)号：US20200072788A1

公开(公告)日：2020-03-05

申请号：US16556689

申请日：2019-08-30

Applicant: IMEC VZW

Inventor： Geert Hellings ,  Koen Martens

IPC: G01N27/414

Abstract: A sensor is provided, the sensor including a field effect transistor comprising: (a) an active region comprising: (i) a source region and a drain region defining a source-drain axis and (ii) a channel region between the source region and the drain region; (b) a dielectric region on the channel region, comprising at least a first zone on a first portion of the channel region and a second zone on a second portion of the channel region, the first zone measuring from 1 to 100 nm in the direction of the source-drain axis and being adapted to create a different threshold voltage for the first portion of the channel region than for the second portion of the channel region, and (c) a fluidic gate region to which a top surface of the dielectric region is exposed. A biosensing device comprising such a sensor, a method for using such a sensor, and a process for making such a sensor are also provided.

公开(公告)号：US20180233570A1

公开(公告)日：2018-08-16

申请号：US15853136

申请日：2017-12-22

Applicant: IMEC VZW

Inventor： Geert Hellings

IPC: H01L29/423 ,  H01L21/8238 ,  H01L21/3065 ,  H01L29/66 ,  H01L21/308 ,  H01L29/06 ,  H01L29/08 ,  H01L29/165 ,  H01L27/092 ,  H01L29/78

CPC classification number: H01L29/42392 ,  H01L21/3065 ,  H01L21/3086 ,  H01L21/3212 ,  H01L21/823431 ,  H01L21/823821 ,  H01L21/823828 ,  H01L27/0886 ,  H01L27/0924 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/7851

Abstract: The disclosed technology generally relates to semiconductor structures and methods of forming the semiconductor structures, and more particularly to semiconductor structures related to a gate-all-around field effect transistor and a fin field effect transistor. In one aspect, a method of forming field effect transistors includes forming in a first region of a substrate a first semiconductor feature and forming in a second region of the substrate a second semiconductor feature. Each of the first and second semiconductor features comprises a fin-shaped semiconductor feature including a vertical stack of at least a first semiconductor material layer and a second semiconductor material layer formed over the first semiconductor material layer. The method additionally includes selectively etching to remove the first semiconductor material layer along a longitudinal section of the first semiconductor feature to form a suspended longitudinal first semiconductor feature of a remaining second semiconductor material layer, while masking the second region to prevent etching of the second semiconductor feature. The method additionally includes forming a gate-all-around electrode surrounding the suspended longitudinal first semiconductor feature in the first region. The method further includes forming a gate electrode on the fin-shaped second semiconductor feature in the second region.

公开(公告)号：US20180013431A1

公开(公告)日：2018-01-11

申请号：US15644614

申请日：2017-07-07

Applicant: IMEC VZW ,  Katholieke Universiteit Leuven

Inventor： Erik Bury ,  Jacopo Franco ,  Geert Hellings ,  Robin Degraeve ,  Benjamin Kaczer

IPC: H03K19/003 ,  H04L9/14 ,  H04L9/08 ,  H01L27/088 ,  H01L27/02 ,  H01L23/00 ,  H01L21/326 ,  H04L9/32 ,  H01L23/528 ,  H03K17/00

CPC classification number: H03K19/003 ,  G09C1/00 ,  H01L21/326 ,  H01L23/528 ,  H01L23/573 ,  H01L27/0203 ,  H01L27/088 ,  H03K17/002 ,  H04L9/0861 ,  H04L9/0866 ,  H04L9/0894 ,  H04L9/14 ,  H04L9/3278

Abstract: A device and a method for implementing a physically unclonable function is disclosed. In one aspect, the device includes at least one electronic structure including a dielectric. A conductive path is formed at a random position through the dielectric due to an electrical breakdown of the dielectric, or the electronic structure is adapted for generating an electrical breakdown of the dielectric such that the conductive path is formed through the dielectric at a random position. The at least one electronic structure is adapted for determining a distinct value of a set comprising at least two predetermined values. The distinct value is determined by the position of the conductive path through the dielectric.

公开(公告)号：US09847336B2

公开(公告)日：2017-12-19

申请号：US15245671

申请日：2016-08-24

Applicant: IMEC VZW

Inventor： Geert Hellings ,  Geert Van der Plas ,  Mirko Scholz

IPC: H01L27/092 ,  H01L21/266 ,  H01L27/06 ,  H01L21/033 ,  H01L29/808 ,  H01L29/66 ,  H01L21/265 ,  H01L21/761 ,  H01L29/10 ,  H01L29/45 ,  H01L29/861

CPC classification number: H01L27/0928 ,  H01L21/0332 ,  H01L21/265 ,  H01L21/266 ,  H01L21/761 ,  H01L27/0629 ,  H01L27/098 ,  H01L29/1058 ,  H01L29/456 ,  H01L29/66128 ,  H01L29/66893 ,  H01L29/66901 ,  H01L29/808 ,  H01L29/8611

Abstract: The disclosed technology relates to semiconductors, and more particularly to a junction field effect transistor (JFET). In one aspect, a method of fabricating a JFET includes forming a well of a first dopant type in a substrate, wherein the well is isolated from the substrate by an isolation region of a second dopant type. The method additionally includes implanting a dopant of the second dopant type at a surface of the well to form a source, a drain and a channel of the JFET, and implanting a dopant of the first dopant type at the surface of the well to form a gate of the JFET. The method additionally includes, prior to implanting the dopant of the first type and the dopant of the second type, forming a pre-metal dielectric (PMD) layer on the well and forming contact openings in the PMD layer above the source, the drain and the gate. The PMD layer has a thickness such that the channel is formed by implanting the dopant of the first type and the dopant of the second type through the PMD layer. The method further includes, after implanting the dopant of the first type and the dopant of the second type, siliciding the source, the drain and the gate, and forming metal contacts in the contact openings.

公开(公告)号：US20170194487A1

公开(公告)日：2017-07-06

申请号：US15389217

申请日：2016-12-22

Applicant: IMEC VZW

Inventor： Shih-Hung Chen ,  Dimitri Linten ,  Geert Hellings

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/08

CPC classification number: H01L29/7816 ,  H01L29/063 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0692 ,  H01L29/0696 ,  H01L29/0847 ,  H01L29/0869 ,  H01L29/0886 ,  H01L29/1095 ,  H01L29/41791 ,  H01L29/7835 ,  H01L29/7851

Abstract: An LDMOS device in FinFET technology is disclosed. In one aspect, the device includes a first region substantially surrounded by a second region of different polarity. The device further includes a first fin in the first region, extending into the second region, the first fin including a doped source region connected with a first local interconnect. The device further includes a second fin in the second region, including a doped drain region connected with a second local interconnect. The device further includes a third fin parallel with the first and second fins including a doped drain region connected with the second local interconnect. The device further includes a gate over the first fin at the border between the first and second regions. A first current path runs over the first and second fins. A second current path runs over and perpendicular to the first fin towards the third fin.