公开(公告)号：US12051465B2

公开(公告)日：2024-07-30

申请号：US17812485

申请日：2022-07-14

Applicant: GlobalFoundries U.S. Inc.

Inventor： Chandrahasa Reddy Dinnipati ,  Bipul C. Paul ,  Ramesh Raghavan

IPC: G11C13/00 ,  G11C11/16

CPC classification number: G11C13/004 ,  G11C11/1673 ,  G11C2013/0054 ,  G11C2213/79

Abstract: Disclosed is a sense circuit with first and second branches connected to first and second inputs of an amplifier. The first branch includes series-connected first transistors between a voltage rail and a data line and a first node between two first transistors and connected to the first input. First transistors on either side of the first node receive corresponding gate bias voltages. The second branch includes series-connected second transistors between the voltage rail and a reference device and a second node between two second transistors and connected to the second input. One first transistor and one second transistor share a common control signal. The first and second branches independently and concurrently generate data and reference voltages on the first and second nodes and the difference between them is sensed by the amplifier. Also disclosed are a non-volatile memory structure incorporating the sense circuit and a method.

公开(公告)号：US20240177770A1

公开(公告)日：2024-05-30

申请号：US18058992

申请日：2022-11-28

Applicant: GlobalFoundries U.S. Inc.

Inventor： Bipul C. Paul ,  Chandrahasa Reddy Dinnipati

IPC: G11C13/00

CPC classification number: G11C13/004 ,  G11C13/0004 ,  G11C13/0026 ,  G11C2013/0042 ,  G11C2213/70

Abstract: A non-volatile memory (NVM) structure includes an array of memory cells. Within the array, data is stored in single cells or twin cells. The structure also includes switch circuits and sense amplifiers. Each switch circuit is connected between bitlines for a group of columns and a corresponding sense amplifier and establishes electrical connections to enable either single cell sensing or twin cell sensing. In single cell sensing, a data signal on a bitline connected to a memory cell is compared to a reference signal. In twin cell sensing, true and complement data signals on two bitlines connected to two memory cells are compared to each other. Since twin cell sensing compares true and complement data signals and does not require a reference signal, twin cell sensing is relatively accurate without the need for trim bits. Thus, the structure can store trim cells, accurately sense them, and subsequently use them.

公开(公告)号：US11881241B2

公开(公告)日：2024-01-23

申请号：US17709525

申请日：2022-03-31

Applicant: GlobalFoundries U.S. Inc.

Inventor： Chandrahasa Reddy Dinnipati ,  Ramesh Raghavan ,  Bipul C. Paul

IPC: G11C11/16 ,  G11C7/06

CPC classification number: G11C11/1673 ,  G11C7/06 ,  G11C11/1655 ,  G11C11/1657 ,  G11C11/1675

Abstract: A structure includes an array of nonvolatile memory cells, wordlines and bitlines connected to the nonvolatile memory cells, sense amplifiers connected to the nonvolatile memory cells, and reference cells connected to the sense amplifiers. Each of the reference cells has a transistor connected to a variable resistor, one of the wordlines, a reference bitline separate from the bitlines, and the sense amplifiers.

公开(公告)号：US20240021243A1

公开(公告)日：2024-01-18

申请号：US17812485

申请日：2022-07-14

Applicant: GlobalFoundries U.S. Inc.

Inventor： Chandrahasa Reddy Dinnipati ,  Bipul C. Paul ,  Ramesh Raghavan

IPC: G11C13/00 ,  G11C11/16

CPC classification number: G11C13/004 ,  G11C11/1673 ,  G11C2213/79 ,  G11C2013/0054

Abstract: Disclosed is a sense circuit with first and second branches connected to first and second inputs of an amplifier. The first branch includes series-connected first transistors between a voltage rail and a data line and a first node between two first transistors and connected to the first input. First transistors on either side of the first node receive corresponding gate bias voltages. The second branch includes series-connected second transistors between the voltage rail and a reference device and a second node between two second transistors and connected to the second input. One first transistor and one second transistor share a common control signal. The first and second branches independently and concurrently generate data and reference voltages on the first and second nodes and the difference between them is sensed by the amplifier. Also disclosed are a non-volatile memory structure incorporating the sense circuit and a method.

公开(公告)号：US20230422519A1

公开(公告)日：2023-12-28

申请号：US17847776

申请日：2022-06-23

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Venkatesh P. Gopinath ,  Joseph Versaggi ,  Gregory A. Northrop ,  Bipul C. Paul

IPC: H01L27/24 ,  G11C5/10 ,  H01L45/00

CPC classification number: H01L27/2436 ,  G11C5/10 ,  H01L45/16

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a capacitor integrated with a memory element of a memory cell and methods of manufacture. The structure includes: at least one memory cell comprising a memory element with a top conductor material; and a capacitor connected to the memory element by the top conductor material.

公开(公告)号：US20230056457A1

公开(公告)日：2023-02-23

申请号：US17445461

申请日：2021-08-19

Applicant: GlobalFoundries U.S. Inc.

Inventor： Bipul C. Paul ,  Shashank S. Nemawarkar

IPC: G11C7/22 ,  G11C7/10

Abstract: Embodiments of the present disclosure provide an apparatus including a memory array including a plurality of sub-arrays. A plurality of temporary storage units (TSUs) is coupled to the plurality of sub-arrays. Each TSU indicates whether the respective sub-array is undergoing one of a read operation and a write operation. A control circuit is coupled to each of the plurality of sub-arrays through a data bus. The control circuit transmits a read pulse or a write pulse as a first pulse with a delay in response to the sub-array undergoing the read operation or the write operation and transmits, instantaneously, the first pulse to one of the plurality of sub-arrays in response to the sub-array not undergoing the read operation or the write operation.

公开(公告)号：US11120857B2

公开(公告)日：2021-09-14

申请号：US16720058

申请日：2019-12-19

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Akhilesh Jaiswal ,  Bipul C. Paul

IPC: G11C11/16 ,  H01L27/22 ,  H01L43/08

Abstract: Disclosed is a reference circuit having an even number m of groups of m parallel-connected magnetic tunnel junctions (MTJs). The MTJs in half of the groups are programmed to have parallel resistances (RP) and the MTJs in the other half are programmed to have anti-parallel resistances (RAP). Switches connect the groups in series, creating a series-parallel resistor network. The total resistance (RT) of the network has low variability and is essentially equal to half the sum of a nominal RP plus a nominal RAP and can be employed as a reference resistance (RREF). Under specific biasing conditions the series-parallel resistor network can generate a low variability reference parameter (XREF) that is dependent on this RREF. Also disclosed are an integrated circuit (IC) that includes the reference circuit and a magnetic random access memory (MRAM) structure, which uses XREF to determine stored data values in MRAM cells and associated methods.

公开(公告)号：US11087814B2

公开(公告)日：2021-08-10

申请号：US16508940

申请日：2019-07-11

Applicant: GLOBALFOUNDRIES U.S. INC.

Inventor： Amogh Agrawal ,  Ajey Poovannummoottil Jacob ,  Bipul C. Paul

IPC: G11C11/16

Abstract: The present disclosure relates to a structure including a non-fixed read-cell circuit configured to switch from a first state to a second state based on a state of a memory cell to generate a sensing margin.

公开(公告)号：US20210240445A1

公开(公告)日：2021-08-05

申请号：US16776909

申请日：2020-01-30

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Hemant M. Dixit ,  Julien Frougier ,  Bipul C. Paul ,  William J. Taylor, JR.

IPC: G06F7/58 ,  G11C11/16

Abstract: Embodiments of the disclosure provide a system for providing a true random number (TRN) or physically unclonable function (PUF), including: an array of voltage controlled magnetic anisotropy (VCMA) cells; a voltage pulse tuning circuit for generating and applying a stochastically tuned voltage pulse to the VCMA cells in the array of VCMA cells, wherein the stochastically tuned voltage pulse has a magnitude and duration that provides a 50%-50% switching distribution of the VCMA cells in the array of VCMA cells; and a bit output system for reading a state of each of the VCMA cells in the array of VCMA cells to provide a TRN or PUF.

公开(公告)号：US20210193204A1

公开(公告)日：2021-06-24

申请号：US16720058

申请日：2019-12-19

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Akhilesh Jaiswal ,  Bipul C. Paul

IPC: G11C11/16 ,  H01L43/08 ,  H01L27/22

Abstract: Disclosed is a reference circuit having an even number m of groups of m parallel-connected magnetic tunnel junctions (MTJs). The MTJs in half of the groups are programmed to have parallel resistances (RP) and the MTJs in the other half are programmed to have anti-parallel resistances (RAP). Switches connect the groups in series, creating a series-parallel resistor network. The total resistance (RT) of the network has low variability and is essentially equal to half the sum of a nominal RP plus a nominal RAP and can be employed as a reference resistance (RREF). Under specific biasing conditions the series-parallel resistor network can generate a low variability reference parameter (XREF) that is dependent on this RREF. Also disclosed are an integrated circuit (IC) that includes the reference circuit and a magnetic random access memory (MRAM) structure, which uses XREF to determine stored data values in MRAM cells and associated methods.