公开(公告)号：US11233006B2

公开(公告)日：2022-01-25

申请号：US16103372

申请日：2018-08-14

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Ruilong Xie ,  Lars Liebmann ,  Daniel Chanemougame ,  Geng Han

IPC: H01L21/768 ,  H01L23/528 ,  H01L23/522 ,  H01L21/02 ,  H01L29/40 ,  H01L21/8238 ,  H01L27/092 ,  H01L27/088 ,  H01L21/8234

Abstract: An integrated circuit product includes a first layer of insulating material including a first insulating material. The first layer of insulating material is positioned above a device layer of a semiconductor substrate. The device layer includes transistors. A metallization blocking structure is positioned in an opening in the first layer of insulating material. The metallization blocking structure includes a second insulating material that is different from the first insulating material. A metallization trench is defined in the first layer of insulating material on opposite sides of the metallization blocking structure. A conductive metallization line includes first and second portions positioned in the metallization trench on opposite sides of the metallization blocking structure. The conductive metallization line has a long axis extending along the first and second portions.

公开(公告)号：US11101348B2

公开(公告)日：2021-08-24

申请号：US16044544

申请日：2018-07-25

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Ruilong Xie ,  Julien Frougier ,  Nigel G. Cave ,  Steven R. Soss ,  Daniel Chanemougame ,  Steven Bentley ,  Rohit Galatage ,  Bum Ki Moon

IPC: H01L29/06 ,  H01L29/66 ,  H01L21/02 ,  H01L21/8234 ,  H01L29/08 ,  H01L21/768 ,  H01L27/088 ,  B82Y40/00 ,  B82Y30/00

Abstract: Methods form devices by creating openings in sacrificial gates between nanosheet stacks (alternating layers of a first material and channel structures), forming spacers in the openings, and removing the sacrificial gates to leave the spacers. The first material is then removed from between the channel structures. A first work function metal is formed around and between the channel structures. Next, first stacks (of the stacks) are protected with a mask to leave second stacks (of the stacks) exposed. Then, the first work function metal is removed from the second stacks while the first stacks are protected by the mask and the spacers. Subsequently, a second work function metal is formed around and between the channel structures of the second stacks. A gate material is then formed over the first work function metal and the second work function metal.

公开(公告)号：US11043588B2

公开(公告)日：2021-06-22

申请号：US16413168

申请日：2019-05-15

Applicant: GLOBALFOUNDRIES U.S. INC.

Inventor： Ali Razavieh ,  Ruilong Xie

IPC: H01L29/78 ,  H01L29/16 ,  H01L27/088 ,  H01L29/66

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a vertical field effect transistor with optimized fin size and improved fin stability and methods of manufacture. The structure includes: a fin structure composed of substrate material, the fin structure includes: a trimmed channel region of the substrate material; a top source/drain region above the trimmed channel region and having a larger cross-section than the trimmed channel region; and a bottom source/drain region below the trimmed channel region and having a larger cross-section than the trimmed channel region; and gate material surrounding the trimmed channel region.

公开(公告)号：US10950610B2

公开(公告)日：2021-03-16

申请号：US16515913

申请日：2019-07-18

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Bipul C. Paul ,  Ruilong Xie ,  Julien Frougier ,  Daniel Chanemougame ,  Hui Zang

IPC: H01L27/11 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/423 ,  H01L29/49 ,  H01L29/786 ,  H01L29/66 ,  H01L21/02 ,  H01L21/28 ,  H01L27/092

Abstract: Methods of forming a gate cut isolation for an SRAM include forming a first and second active nanostructures adjacent to each other and separated by a space; forming a sacrificial liner over at least a side of the first active nanostructure facing the space, causing a first distance between a remaining portion of the space and the first active nanostructure to be greater than a second distance between the remaining portion of the space and the second active nanostructure. A gate cut isolation is formed in the remaining portion of the space such that it is closer to the second active nanostructure than the first active nanostructure. The sacrificial liner is removed, and gates formed over the active nanostructures with the gates separated from each other by the gate cut isolation. An SRAM including the gate cut isolation and an IC structure including the SRAM are also included.

公开(公告)号：US12131994B2

公开(公告)日：2024-10-29

申请号：US18362044

申请日：2023-07-31

Applicant: GlobalFoundries U.S. Inc.

Inventor： Ruilong Xie ,  Lars Liebmann ,  Daniel Chanemougame ,  Geng Han

IPC: H01L23/528 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H01L21/02 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/088 ,  H01L27/092 ,  H01L29/40

CPC classification number: H01L23/5283 ,  H01L21/76802 ,  H01L21/76816 ,  H01L23/5226 ,  H01L23/53295 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/76814 ,  H01L21/76832 ,  H01L21/76835 ,  H01L21/76861 ,  H01L21/76877 ,  H01L21/76879 ,  H01L21/823431 ,  H01L21/823821 ,  H01L27/0886 ,  H01L27/0924 ,  H01L29/401

Abstract: An integrated circuit product includes a first layer of insulating material above a device layer of a semiconductor substrate and with a lowermost surface above an uppermost surface of a gate of a transistor in a device layer of the semiconductor substrate. A metallization blocking structure is in an opening in the first layer of insulating material and has a lowermost surface above the uppermost surface of the gate and includes a second insulating material that is different from the first insulating material. A metallization trench is in the first layer of insulating material on opposite sides of the metallization blocking structure. A contact structure is in the second insulating material and entirely below the metallization trench. A conductive metallization line includes first and second portions positioned in the metallization trench on opposite sides of the metallization blocking structure and a long axis extending along the first and second portions.

公开(公告)号：US20240339538A1

公开(公告)日：2024-10-10

申请号：US18749813

申请日：2024-06-21

Applicant: GlobalFoundries U.S. Inc.

Inventor： Julien Frougier ,  Ruilong Xie ,  Kangguo Cheng ,  Chanro Park

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/165 ,  H01L29/66

CPC classification number: H01L29/785 ,  H01L29/0649 ,  H01L29/0673 ,  H01L29/165 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/6656 ,  H01L29/66795

Abstract: Disclosed are a gate-all-around field effect transistor (GAAFET) and method. The GAAFET includes stacked nanosheets having end portions adjacent to source/drain regions and a center portion between the end portions. The thickness of each nanosheet is tapered from a maximum thickness near the source/drain regions to a minimum thickness near and across the center portion. A gate wraps around each center portion. Inner spacers are aligned below the end portions between the gate and source/drain regions. The thickness of each inner spacer is tapered from a maximum thickness at the gate to a minimum thickness near the adjacent source/drain region. Each inner spacer includes a first spacer layer immediately adjacent to the gate, a second spacer layer immediately adjacent to the gate at least above the first spacer layer and further extending laterally beyond the first spacer layer toward or to the adjacent source/drain region, and, optionally, an air-gap.

公开(公告)号：US12094972B2

公开(公告)日：2024-09-17

申请号：US16406071

申请日：2019-05-08

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Julien Frougier ,  Ruilong Xie ,  Kangguo Cheng ,  Chanro Park

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/165 ,  H01L29/66

CPC classification number: H01L29/785 ,  H01L29/0649 ,  H01L29/0673 ,  H01L29/165 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/6656 ,  H01L29/66795

Abstract: Disclosed are a gate-all-around field effect transistor (GAAFET) and method. The GAAFET includes stacked nanosheets having end portions adjacent to source/drain regions and a center portion between the end portions. The thickness of each nanosheet is tapered from a maximum thickness near the source/drain regions to a minimum thickness near and across the center portion. A gate wraps around each center portion. Inner spacers are aligned below the end portions between the gate and source/drain regions. The thickness of each inner spacer is tapered from a maximum thickness at the gate to a minimum thickness near the adjacent source/drain region. Each inner spacer includes a first spacer layer immediately adjacent to the gate, a second spacer layer immediately adjacent to the gate at least above the first spacer layer and further extending laterally beyond the first spacer layer toward or to the adjacent source/drain region, and, optionally, an air-gap.

公开(公告)号：US12002869B2

公开(公告)日：2024-06-04

申请号：US17901887

申请日：2022-09-02

Applicant: GlobalFoundries U.S. Inc.

Inventor： Ruilong Xie ,  Youngtag Woo ,  Daniel Chanemougame ,  Bipul C. Paul ,  Lars W. Liebmann ,  Heimanu Niebojewski ,  Xuelian Zhu ,  Lei Sun ,  Hui Zang

IPC: H01L29/49 ,  H01L21/28 ,  H01L21/8234 ,  H01L27/088 ,  H01L27/092 ,  H01L29/417 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/4975 ,  H01L21/28 ,  H01L21/823431 ,  H01L21/823475 ,  H01L27/0886 ,  H01L27/092 ,  H01L29/41775 ,  H01L29/66477 ,  H01L29/783

Abstract: One illustrative integrated circuit (IC) product disclosed herein includes a first conductive source/drain contact structure of a first transistor with an insulating source/drain cap positioned above at least a portion of an upper surface of the first conductive source/drain contact structure and a gate-to-source/drain (GSD) contact structure that is conductively coupled to the first conductive source/drain contact structure and a first gate structure of a second transistor. In this example, the product also includes a gate contact structure that is conductively coupled to a second gate structure of a third transistor, wherein an upper surface of each of the GSD contact structure and the gate contact structure is positioned at a first level that is at a level that is above a level of an upper surface of the insulating source/drain cap.

公开(公告)号：US11810812B2

公开(公告)日：2023-11-07

申请号：US17382645

申请日：2021-07-22

Applicant: GLOBALFOUNDRIES U.S. INC.

Inventor： Hui Zang ,  Ruilong Xie ,  Jessica M. Dechene

IPC: H01L21/762 ,  H01L29/66 ,  H01L21/308 ,  H01L27/088

CPC classification number: H01L21/76232 ,  H01L21/3086 ,  H01L27/0886 ,  H01L29/66545 ,  H01L29/66795

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to single diffusion cut for gate structures and methods of manufacture. The structure includes a single diffusion break extending into a substrate between diffusion regions of adjacent gate structures, the single diffusion break filled with an insulator material and further comprising an undercut region lined with a liner material which is between the insulator material and the diffusion regions.

公开(公告)号：US20220416054A1

公开(公告)日：2022-12-29

申请号：US17901887

申请日：2022-09-02

Applicant: GlobalFoundries U.S. Inc.

Inventor： Ruilong Xie ,  Youngtag Woo ,  Daniel Chanemougame ,  Bipul C. Paul ,  Lars W. Liebmann ,  Heimanu Niebojewski ,  Xuelian Zhu ,  Lei Sun ,  Hui Zang

IPC: H01L29/49 ,  H01L21/8234 ,  H01L29/417 ,  H01L29/66 ,  H01L29/78 ,  H01L21/28 ,  H01L27/088 ,  H01L27/092

Abstract: One illustrative integrated circuit (IC) product disclosed herein includes a first conductive source/drain contact structure of a first transistor with an insulating source/drain cap positioned above at least a portion of an upper surface of the first conductive source/drain contact structure and a gate-to-source/drain (GSD) contact structure that is conductively coupled to the first conductive source/drain contact structure and a first gate structure of a second transistor. In this example, the product also includes a gate contact structure that is conductively coupled to a second gate structure of a third transistor, wherein an upper surface of each of the GSD contact structure and the gate contact structure is positioned at a first level that is at a level that is above a level of an upper surface of the insulating source/drain cap.