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公开(公告)号：US06872643B1
公开(公告)日：2005-03-29
申请号：US10378885
申请日：2003-03-05
IPC分类号： H01L21/265 , H01L21/268 , H01L21/22
CPC分类号： H01L21/265 , H01L21/268 , Y10S438/914
摘要： A method of manufacturing a semiconductor device includes forming a layer over a substrate, and doping the layer with a dopant, after which the layer is laser thermal annealed. The layer can be a nitride, an oxide, or a polysilicon layer. The dopants can be arsenic, phosphorous, boron, or nitrogen. During the laser thermal annealing, certain portions of a surface of the semiconductor device are laser thermal annealed and other portions of a surface of the semiconductor device are not exposed. Also, the surface of the layer is smoother after the laser thermal annealing.
摘要翻译： 制造半导体器件的方法包括在衬底上形成层，并用掺杂剂掺杂该层，之后激光热退火。 该层可以是氮化物，氧化物或多晶硅层。 掺杂剂可以是砷，磷，硼或氮。 在激光热退火期间，半导体器件的表面的某些部分被激光热退火，并且半导体器件的表面的其它部分不被暴露。 此外，在激光热退火之后，该层的表面更平滑。
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22.发明授权公开(公告)号：US06783591B1
公开(公告)日：2004-08-31
申请号：US10212237
申请日：2002-08-06
IPC分类号： C30B2504
CPC分类号： H01L29/6659 , H01L21/268 , H01L21/28194 , H01L21/28202 , H01L21/31604 , H01L21/31637 , H01L21/31641 , H01L21/31645 , H01L21/31691 , H01L29/517 , H01L29/518 , H01L29/665
摘要： A method of manufacturing a semiconductor device, including depositing a gate oxide film over a substrate and conditioning the deposited gate oxide film using laser thermal annealing in a single process chamber, and depositing a gate electrode film over the conditioned gate oxide film.
摘要翻译： 一种制造半导体器件的方法，包括在衬底上沉积栅极氧化膜并在单个处理室中使用激光热退火调节沉积的栅极氧化膜，并在调节的栅极氧化物膜上沉积栅电极膜。
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23.发明授权Use of high-k dielectric materials in modified ONO structure for semiconductor devices 有权用于半导体器件的改性ONO结构中的高k电介质材料公开(公告)号：US06674138B1
公开(公告)日：2004-01-06
申请号：US10036757
申请日：2001-12-31
IPC分类号： H01L2976
CPC分类号： H01L21/28185 , H01L21/28194 , H01L21/28202 , H01L21/28211 , H01L21/28282 , H01L29/513 , H01L29/517 , H01L29/518 , H01L29/66833 , H01L29/7923
摘要： A process for fabrication of a semiconductor device including a modified ONO structure, including forming the modified ONO structure by providing a semiconductor substrate; forming a first oxide layer on the semiconductor substrate; depositing a layer comprising a high-K dielectric material on the first oxide layer; and forming a top oxide layer on the layer comprising a high-K dielectric material. The semiconductor device may be, e.g., a MIRRORBIT™ two-bit EEPROM device or a floating gate flash device including a modified ONO structure.
摘要翻译： 一种制造包括改性ONO结构的半导体器件的方法，包括通过提供半导体衬底形成修饰的ONO结构; 在所述半导体衬底上形成第一氧化物层; 在所述第一氧化物层上沉积包含高K电介质材料的层; 以及在包含高K电介质材料的层上形成顶部氧化物层。 半导体器件可以是例如MIRRORBIT TM 2位EEPROM器件或包括修改的ONO结构的浮动栅极闪存器件。
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公开(公告)号：US06670241B1
公开(公告)日：2003-12-30
申请号：US10128771
申请日：2002-04-22
申请人： Tazrien Kamal , Arvind Halliyal , Minh Van Ngo , Mark T. Ramsbey , Jean Y. Yang , Hidehiko Shiraiwa , Rinji Sugino
发明人： Tazrien Kamal , Arvind Halliyal , Minh Van Ngo , Mark T. Ramsbey , Jean Y. Yang , Hidehiko Shiraiwa , Rinji Sugino
IPC分类号： H01L21336
CPC分类号： H01L27/11568 , H01L29/66833
摘要： A device and method for manufacturing thereof for a MirrorBit® Flash memory includes providing a semiconductor substrate and successively depositing a first insulating layer, a charge-trapping layer, and a second insulating layer. First and second bitlines are implanted and wordlines are formed before completing the memory. Spacers are formed between the wordlines and an inter-layer dielectric layer is formed over the wordlines. One or more of the second insulating layer, wordlines, spacers, and inter-layer dielectric layers are deuterated, replacing hydrogen bonds with deuterium, thus improving data retention and substantially reducing charge loss.
摘要翻译： 用于制造MirrorBit（闪存）闪存的器件及其制造方法包括：提供半导体衬底，并依次沉积第一绝缘层，电荷俘获层和第二绝缘层。 植入第一和第二位线，并在完成内存之前形成字线。 在字线之间形成间隔，并且在字线之间形成层间电介质层。 第二绝缘层，字线，间隔层和层间电介质层中的一个或多个被氘化，用氘替代氢键，从而改善数据保留并显着降低电荷损失。
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公开(公告)号：US06667243B1
公开(公告)日：2003-12-23
申请号：US10222248
申请日：2002-08-16
IPC分类号： H01L21302
CPC分类号： H01L21/02071 , H01L21/31138 , H01L21/32137 , H01L21/32139 , H01L29/6659 , Y10S438/906 , Y10S438/94
摘要： A method of manufacturing a semiconductor device etches a feature on a substrate in accordance with a photoresist mask. The photoresist mask is removed by plasma etching. Laser thermal annealing is performed to vaporize polymer residue created during the stripping of the photoresist mask, and to repair damage to the substrate.
摘要翻译： 半导体器件的制造方法根据光致抗蚀剂掩模蚀刻衬底上的特征。 通过等离子体蚀刻去除光致抗蚀剂掩模。 进行激光热退火以蒸发在光刻胶掩模剥离期间产生的聚合物残余物，并修复对基材的损伤。
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公开(公告)号：US06653191B1
公开(公告)日：2003-11-25
申请号：US10151576
申请日：2002-05-16
申请人： Jean Y. Yang , Arvind Halliyal , Amir H. Jafarpour , Tazrien Kamal , Mark T. Ramsbey , Emmanuil Lingunis , Hidehiko Shiraiwa
发明人： Jean Y. Yang , Arvind Halliyal , Amir H. Jafarpour , Tazrien Kamal , Mark T. Ramsbey , Emmanuil Lingunis , Hidehiko Shiraiwa
IPC分类号： H01L218247
CPC分类号： H01L27/11568 , H01L27/105 , H01L27/115 , H01L27/11573
摘要： A method of manufacturing an integrated circuit includes providing a semiconductor substrate and depositing a charge-trapping dielectric layer and a gate dielectric layer over the semiconductor substrate. Bitlines are implanted closely in the semiconductor substrate and annealed using a rapid thermal anneal. Wordlines and gates are formed and source/drain junctions are implanted in the semiconductor substrate. An interlayer dielectric layer is deposited and the integrated circuit completed.
摘要翻译： 集成电路的制造方法包括提供半导体衬底，并在半导体衬底上沉积电荷俘获电介质层和栅介质层。 位线在半导体衬底中紧密地植入，并使用快速热退火退火。 形成字线和栅极，并且将源极/漏极结注入到半导体衬底中。 沉积层间电介质层并完成集成电路。
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公开(公告)号：US06730564B1
公开(公告)日：2004-05-04
申请号：US10217821
申请日：2002-08-12
申请人： Mark T. Ramsbey , Yu Sun , Chi Chang , Hidehiko Shiraiwa
发明人： Mark T. Ramsbey , Yu Sun , Chi Chang , Hidehiko Shiraiwa
IPC分类号： H01L218247
CPC分类号： H01L27/11568 , H01L27/105 , H01L27/115 , H01L27/11526 , H01L27/11534 , Y10S438/954
摘要： The present invention provides a process for saliciding word lines in a virtual ground array flash memory device without causing shorting between bit lines. According to one aspect of the invention, saliciding takes place prior to patterning one or more layers of a memory cell stack. The unpatterned layers protect the substrate between word lines from becoming salicided. The invention provides virtual ground array flash memory devices with doped and salicided word lines, but no shorting between bit lines, even in virtual ground arrays where there are no oxide island isolation regions between word lines. Potential advantages of such structures include reduced size, reduced number of processing steps, and reduced exposure to high temperature cycling.
摘要翻译： 本发明提供了一种在虚拟接地阵列闪存器件中对字线进行水印处理，而不引起位线之间的短路。 根据本发明的一个方面，在对存储单元堆叠的一层或多层进行构图之前进行水化。 未图案化的层保护字线之间的基板不会变成水银。 本发明提供具有掺杂和含水字线的虚拟接地阵列闪存器件，但是即使在字线之间没有氧化物岛隔离区域的虚拟接地阵列中也不会在位线之间发生短路。 这种结构的潜在优点包括减小的尺寸，减少的加工步骤数量以及降低暴露于高温循环。
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28.发明授权公开(公告)号：US06720133B1
公开(公告)日：2004-04-13
申请号：US10126280
申请日：2002-04-19
申请人： Mark T. Ramsbey , Kouros Ghandehari , Tazrien Kamal , Jean Y. Yang , Emmanuil Lingunis , Hidehiko Shiraiwa
发明人： Mark T. Ramsbey , Kouros Ghandehari , Tazrien Kamal , Jean Y. Yang , Emmanuil Lingunis , Hidehiko Shiraiwa
IPC分类号： G03F700
CPC分类号： H01L27/11568 , H01L27/115 , Y10S430/151
摘要： A method of manufacturing an integrated circuit includes a semiconductor substrate having bitlines under a charge-trapping material over a core region and a gate insulator material over a periphery region. A wordline-gate material, a hard mask, and a first photoresist are deposited and patterned over the core region while covering the periphery region. After removing the first photoresist, wordlines are formed from the wordline-gate material in the core region. An anti-reflective coating and a second photoresist are deposited and patterned over the periphery region and covering the core region. The anti-reflective coating is removable without damaging the charge-trapping material. After removing the second photoresist and the anti-reflective coating, gates are formed from the wordline-gate material in the periphery region and the integrated circuit completed.
摘要翻译： 集成电路的制造方法包括在芯区域上的电荷捕获材料下方具有位线的半导体衬底和在周边区域上的栅极绝缘体材料。 在覆盖周边区域的同时，在芯区域上沉积并图案化字线栅极材料，硬掩模和第一光致抗蚀剂。 在去除第一光致抗蚀剂之后，从芯区域中的字线栅极材料形成字线。 在外围区域上沉积并图案化抗反射涂层和第二光致抗蚀剂并覆盖芯区域。 防反射涂层是可去除的，而不会损坏电荷捕获材料。 在去除第二光致抗蚀剂和抗反射涂层之后，栅极由周边区域中的字线栅极材料形成，并且集成电路完成。
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29.发明授权公开(公告)号：US06630384B1
公开(公告)日：2003-10-07
申请号：US09971483
申请日：2001-10-05
申请人： Yu Sun , Michael A. Van Buskirk , Mark T. Ramsbey
发明人： Yu Sun , Michael A. Van Buskirk , Mark T. Ramsbey
IPC分类号： H01L21336
CPC分类号： H01L27/11568 , H01L27/115
摘要： One aspect of the present invention relates to a method of forming a non-volatile semiconductor memory device, involving forming a charge trapping dielectric over a substrate, the substrate having a core region and a periphery region; forming a first set of memory cell gates over the charge trapping dielectric in the core region; forming a conformal insulation material layer around the first set of memory cell gates; and forming a second set of memory cell gates in the core region, wherein each memory cell gate of the second set of memory cell gates is adjacent to at least one memory cell gate of the first set of memory cell gates, each memory cell gate of the first set of memory cell gates is adjacent at least one memory cell gate of the second set of memory cell gates, and the conformal insulation material layer is positioned between each adjacent memory cell gate.
摘要翻译： 本发明的一个方面涉及一种形成非易失性半导体存储器件的方法，包括在衬底上形成电荷俘获电介质，所述衬底具有芯区域和外围区域; 在芯区域中的电荷俘获电介质上形成第一组存储单元栅极; 在所述第一组存储单元栅极周围形成保形绝缘材料层; 以及在所述核心区域中形成第二组存储器单元栅极，其中所述第二组存储单元栅极的每个存储单元栅极与所述第一组存储单元栅极的至少一个存储单元栅极相邻， 第一组存储单元栅极与第二组存储单元栅极的至少一个存储单元栅极相邻，并且保形绝缘材料层位于每个相邻的存储单元栅极之间。
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30.发明授权Bi-layer floating gate for improved work function between floating gate and a high-K dielectric layer 有权双层浮栅，用于改善浮栅和高K电介质层之间的功函数公开(公告)号：US06630383B1
公开(公告)日：2003-10-07
申请号：US10274063
申请日：2002-10-17
IPC分类号： H01L21336
CPC分类号： H01L21/28194 , H01L21/28273 , H01L29/42324 , H01L29/4958 , H01L29/51 , H01L29/511
摘要： In one embodiment, a method of making a gate stack semiconductor device is disclosed. The method comprises the steps of: forming a tunnel oxide layer over a p-type semiconductor substrate; forming a floating gate over the tunnel oxide layer by first forming an n-type polysilicon layer and subjecting the n-type polysilicon layer to nitridation, and then forming a p-type polysilicon layer over the nitridated n-type polysilicon layer; and forming a high-K insulating layer over the p-type polysilicon layer.
摘要翻译： 在一个实施例中，公开了制造栅叠层半导体器件的方法。 该方法包括以下步骤：在p型半导体衬底上形成隧道氧化物层; 通过首先形成n型多晶硅层并对n型多晶硅层进行氮化，然后在氮化的n型多晶硅层上形成p型多晶硅层，在隧道氧化物层上形成浮栅; 以及在p型多晶硅层上形成高K绝缘层。
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