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    PERFORMING CONCURRENT DIFFUSION BREAK, GATE AND SOURCE/DRAIN CONTACT CUT ETCH PROCESSES
    22.
    发明申请
    PERFORMING CONCURRENT DIFFUSION BREAK, GATE AND SOURCE/DRAIN CONTACT CUT ETCH PROCESSES 审中-公开

    公开(公告)号：US20190326177A1

    公开(公告)日：2019-10-24

    申请号：US15958593

    申请日：2018-04-20

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Laertis Economikos ,  Hui Zang ,  Ruilong Xie ,  Haiting Wang ,  Hong Yu

    IPC: H01L21/8234 ,  H01L21/762 ,  H01L29/66

    Abstract: A device is formed including fins formed above a substrate, an isolation structure between the fins, a plurality of structures defining gate cavities, and a first dielectric material positioned between the structures. A patterning layer above the first dielectric material and in the gate cavities has a first opening positioned above a first gate cavity exposing a portion of the isolation structure and defining a first recess, a second opening above a second gate cavity exposing a first portion of the fins, and a third opening above a first portion of a source/drain region in the fins to expose the first dielectric material. Using the patterning layer, a second recess is formed in the substrate and a third recess is defined in the first dielectric material. A second dielectric material is formed in the recesses to define a gate cut structure, a diffusion break structure, and a contact cut structure.

    FINFET WITH HIGH-K SPACER AND SELF-ALIGNED CONTACT CAPPING LAYER
    23.
    发明申请
    FINFET WITH HIGH-K SPACER AND SELF-ALIGNED CONTACT CAPPING LAYER 审中-公开

    公开(公告)号：US20190259619A1

    公开(公告)日：2019-08-22

    申请号：US15902098

    申请日：2018-02-22

    Applicant: GLOBALFOUNDRIES INC.

    Inventor： Hui Zang ,  Guowei Xu ,  Keith Tabakman

    IPC: H01L21/28 ,  H01L29/78 ,  H01L29/49 ,  H01L23/535 ,  H01L29/66 ,  H01L21/768

    Abstract: In the manufacture of a FinFET device, an isolation architecture is provided between gate and source/drain contact locations. The isolation architecture may include a low-k spacer layer and a contact etch stop layer. The isolation architecture further includes a high-k, etch-selective layer that is adapted to resist degradation during an etch to open the source/drain contact locations. The high-k layer, in conjunction with a self-aligned contact (SAC) capping layer disposed over the gate, forms an improved isolation structure that inhibits short circuits or parasitic capacitance between the gate and source/drain contacts.

    Methods of forming a gate contact structure for a transistor
    24.
    发明授权
    Methods of forming a gate contact structure for a transistor 有权

    公开(公告)号：US10297452B2

    公开(公告)日：2019-05-21

    申请号：US15712301

    申请日：2017-09-22

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Ruilong Xie ,  Hui Zang ,  Kangguo Cheng ,  Tenko Yamashita ,  Chun-Chen Yeh

    IPC: H01L29/78 ,  H01L21/28 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66

    Abstract: One illustrative method disclosed includes selectively forming sacrificial conductive source/drain cap structures on and in contact with first and second source/drain contact structures positioned on opposite sides of a gate of a transistor and removing and replacing the spaced-apart sacrificial conductive source/drain cap structures with first and second separate, laterally spaced-apart insulating source/drain cap structures that are positioned on the first and second source/drain contact structures. The method also includes forming a gate contact opening that extends through a space between the insulating source/drain cap structures and through the gate cap so as to expose a portion of the gate structure and forming a conductive gate contact structure (CB) that is conductively coupled to the gate structure.

    FORMING CONTACTS FOR VFETS
    25.
    发明申请
    FORMING CONTACTS FOR VFETS 审中-公开

    公开(公告)号：US20190148494A1

    公开(公告)日：2019-05-16

    申请号：US15814724

    申请日：2017-11-16

    Applicant: GLOBALFOUNDRIES INC.

    Inventor： Ruilong Xie ,  Lars Liebmann ,  Daniel Chanemougame ,  Chanro Park ,  John H. Zhang ,  Steven Bentley ,  Hui Zang

    IPC: H01L29/10 ,  H01L29/78 ,  H01L27/24 ,  H01L21/8234

    Abstract: A first vertical field effect transistor (VFET) and a second VFET are formed on a substrate. The VFETs are parallel and adjacent to one another, and each comprises: a fin-shaped semiconductor; a lower source/drain (S/D) element; an upper S/D element; and a gate conductor. A portion of a gate conductor of the second VFET that is positioned over a lower S/D element of the second VFET is removed to leave a trench. An isolation spacer is formed to contact the gate conductor of the second VFET in a first portion of the trench. A lower S/D contact of the second VFET is formed on the lower S/D element of the second VFET in a second portion of the trench, a lower S/D contact of the first VFET is formed to a lower S/D element of the first VFET, and contacts are formed.

    LDMOS FINFET STRUCTURES WITH SHALLOW TRENCH ISOLATION INSIDE THE FIN
    26.
    发明申请
    LDMOS FINFET STRUCTURES WITH SHALLOW TRENCH ISOLATION INSIDE THE FIN 审中-公开

    公开(公告)号：US20190131406A1

    公开(公告)日：2019-05-02

    申请号：US15797606

    申请日：2017-10-30

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Jerome Ciavatti ,  Jagar Singh ,  Hui Zang

    IPC: H01L29/10 ,  H01L29/78 ,  H01L29/06 ,  H01L29/66 ,  H01L21/762

    Abstract: Field-effect transistor structures for a laterally-diffused metal-oxide-semiconductor (LDMOS) device and methods of forming a LDMOS device. First and second fins are formed that extend vertically from a top surface of a substrate. A body region is arranged partially in the substrate and partially in the first fin. A drain region is arranged partially in the substrate, partially in the first fin, and partially in the second fin. The body and drain regions respectively have opposite first and second conductivity types. A source region of the second conductivity type is located within the first well in the first fin, and a gate structure is arranged to overlap with a portion of the first fin. The first fin is separated from the second fin by a cut extending vertically to the top surface of the substrate. An isolation region is arranged in the cut between the first fin and the second fin.

    Self-aligned gate caps with an inverted profile
    27.
    发明授权
    Self-aligned gate caps with an inverted profile 有权

    公开(公告)号：US10276391B1

    公开(公告)日：2019-04-30

    申请号：US16007127

    申请日：2018-06-13

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Hui Zang ,  Ruilong Xie ,  Laertis Economikos

    IPC: H01L21/28 ,  H01L29/423 ,  H01L21/8234 ,  H01L29/66 ,  H01L29/417

    Abstract: Structures for a field-effect transistor and methods of forming a structure for field-effect transistor. A gate structure includes a work function metal layer, a first conductor layer, and a second conductor layer arranged over the work function metal layer. The second conductor layer has a sidewall and a top surface, and the first conductor layer has a first section arranged between the second conductor layer and the work function metal layer and a second section arranged adjacent to a first portion of the sidewall of the second conductor layer. A dielectric cap is arranged on the gate structure. The dielectric cap has a first section arranged over the top surface of the second conductor layer and a second section arranged adjacent to a second portion of the sidewall of the second conductor layer.

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