公开(公告)号：US20100128531A1

公开(公告)日：2010-05-27

申请号：US12617972

申请日：2009-11-13

申请人： Changhyun Lee ,  Jungdal Choi ,  Yoocheol Shin ,  Yongsik Yim

发明人： Changhyun Lee ,  Jungdal Choi ,  Yoocheol Shin ,  Yongsik Yim

IPC分类号： G11C16/04 ,  G11C11/34

CPC分类号： G11C16/0466

摘要： A nonvolatile memory device includes a word line group including a plurality of middle word lines and an edge word line having charge storage patterns on a substrate. A peripheral line is disposed on one side of the word line group so that the edge word line is between the peripheral word line and the middle word lines. The peripheral line includes an insulating layer and a gate electrode. Charge storage patterns of the middle and edge word lines are separated from each other, and a charge storage pattern of the edge word line extends on one side to be connected to the insulating layer of the peripheral line. Methods of forming nonvolatile memory devices are also disclosed.

摘要翻译： 非易失性存储器件包括一个包括多个中间字线的字线组和在衬底上具有电荷存储图案的边缘字线。 外围线设置在字线组的一侧，使得边缘字线在周边字线和中间字线之间。 外围线包括绝缘层和栅电极。 中间和边缘字线的电荷存储模式彼此分离，并且边缘字线的电荷存储模式在一侧延伸以连接到外围线的绝缘层。 还公开了形成非易失性存储器件的方法。

公开(公告)号：US09224493B2

公开(公告)日：2015-12-29

申请号：US14280920

申请日：2014-05-19

申请人： Changhyun Lee ,  Jungdal Choi ,  Byeong-In Choe

发明人： Changhyun Lee ,  Jungdal Choi ,  Byeong-In Choe

IPC分类号： G11C16/26 ,  G11C16/30 ,  G11C16/34 ,  G11C8/10 ,  G11C11/56 ,  G11C16/04 ,  G11C29/00

CPC分类号： G11C16/26 ,  G11C8/10 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/3418 ,  G11C16/3436 ,  G11C16/3454 ,  G11C16/3459 ,  G11C29/00

摘要： A nonvolatile memory device has improved reliability by compensating a threshold voltage of a flash memory cell. A nonvolatile memory device includes a memory cell array and a voltage generator for supplying a select read voltage to a select word line and an unselect read voltage to unselected word lines when a read operation is performed, and supplying a verify voltage to a select word line and the unselect read voltage to unselected word lines when a program operation is performed. The voltage generator supplies a first unselect read voltage to at least one between an upper word line and a lower word line adjacent to the select word line when the program operation is performed, and supplies a second unselected read voltage to at least one between the upper word line and the lower word line adjacent to the select word line when the read operation is performed.

摘要翻译： 非易失性存储器件通过补偿闪存单元的阈值电压而提高了可靠性。 非易失性存储器件包括：存储单元阵列和电压发生器，用于在执行读取操作时将选择读取电压提供给选择字线，并将未选择读取电压提供给未选择的字线;以及将验证电压提供给选择字线 以及当执行编程操作时，对未选字线的取消选择读取电压。 电压发生器在执行编程操作时将第一未读选择电压提供给与选择字线相邻的上字线和下字线之间的至少一个，并且将第二未选择读电压提供给上 当执行读操作时，字线和与选择字线相邻的下字线。

公开(公告)号：US08829589B2

公开(公告)日：2014-09-09

申请号：US13757273

申请日：2013-02-01

申请人： Changhyun Lee ,  Byoungkeun Son ,  Youngwoo Park

发明人： Changhyun Lee ,  Byoungkeun Son ,  Youngwoo Park

IPC分类号： H01L29/788 ,  H01L29/04 ,  H01L29/792

CPC分类号： H01L29/788 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/11578 ,  H01L29/04 ,  H01L29/7889 ,  H01L29/792 ,  H01L29/7926

摘要： A three-dimensional semiconductor memory device may include gap-fill insulating layers extending upward from a substrate, an electrode structure delimited by sidewalls of the gap-fill insulating layers, vertical structures provided between adjacent ones of the gap-fill insulating layers to penetrate the electrode structure, and at least one separation pattern extending along the gap-fill insulating layers and penetrating at least a portion of the electrode structure. The separation pattern may include at least one separation semiconductor layer.

摘要翻译： 三维半导体存储器件可以包括从衬底向上延伸的间隙填充绝缘层，由间隙填充绝缘层的侧壁限定的电极结构，设置在相邻的间隙填充绝缘层之间的垂直结构以穿透 电极结构，以及沿间隙填充绝缘层延伸并穿透电极结构的至少一部分的至少一个分离图案。 分离图案可以包括至少一个分离半导体层。

公开(公告)号：US08581321B2

公开(公告)日：2013-11-12

申请号：US13281612

申请日：2011-10-26

申请人： Byoungkeun Son ,  Changhyun Lee ,  Jaegoo Lee ,  Kwang Soo Seol ,  Byungkwan You

发明人： Byoungkeun Son ,  Changhyun Lee ,  Jaegoo Lee ,  Kwang Soo Seol ,  Byungkwan You

IPC分类号： H01L29/792 ,  H01L29/76

CPC分类号： H01L29/66833 ,  H01L27/11582 ,  H01L29/7926

摘要： A nonvolatile memory device and a method of forming the same, the device including a semiconductor substrate; a plurality of gate patterns stacked on the semiconductor substrate; inter-gate dielectric patterns between the gate patterns; active pillars sequentially penetrating the gate patterns and the inter-gate dielectric patterns to contact the semiconductor substrate; and a gate insulating layer between the active pillars and the gate patterns, wherein corners of the gate patterns adjacent to the active pillars are rounded.

摘要翻译： 非易失性存储器件及其形成方法，所述器件包括半导体衬底; 堆叠在所述半导体衬底上的多个栅极图案; 栅极图案之间的栅极间电介质图案; 依次穿过栅极图案和栅极间电介质图案以接触半导体衬底的有源支柱; 以及在活性柱和栅极图案之间的栅极绝缘层，其中与活性柱相邻的栅极图案的角部是圆形的。

公开(公告)号：US08064259B2

公开(公告)日：2011-11-22

申请号：US12617972

申请日：2009-11-13

申请人： Changhyun Lee ,  Jungdal Choi ,  Yoocheol Shin ,  Yongsik Yim

发明人： Changhyun Lee ,  Jungdal Choi ,  Yoocheol Shin ,  Yongsik Yim

IPC分类号： G11C11/34

CPC分类号： G11C16/0466

摘要： A nonvolatile memory device includes a word line group including a plurality of middle word lines and an edge word line having charge storage patterns on a substrate. A peripheral line is disposed on one side of the word line group so that the edge word line is between the peripheral word line and the middle word lines. The peripheral line includes an insulating layer and a gate electrode. Charge storage patterns of the middle and edge word lines are separated from each other, and a charge storage pattern of the edge word line extends on one side to be connected to the insulating layer of the peripheral line. Methods of forming nonvolatile memory devices are also disclosed.

摘要翻译： 非易失性存储器件包括一个包括多个中间字线的字线组和在衬底上具有电荷存储图案的边缘字线。 外围线设置在字线组的一侧，使得边缘字线在周边字线和中间字线之间。 外围线包括绝缘层和栅电极。 中间和边缘字线的电荷存储模式彼此分离，并且边缘字线的电荷存储模式在一侧延伸以连接到外围线的绝缘层。 还公开了形成非易失性存储器件的方法。

公开(公告)号：US08059466B2

公开(公告)日：2011-11-15

申请号：US12656083

申请日：2010-01-15

申请人： Changhyun Lee ,  Jungdal Choi ,  Byeong-In Choe

发明人： Changhyun Lee ,  Jungdal Choi ,  Byeong-In Choe

IPC分类号： G11C16/04

CPC分类号： G11C16/26 ,  G11C11/5642

摘要： Provided are a non-volatile memory system and a programming method thereof. The programming method of the non-volatile memory system includes adjusting a program-verify-voltage of a selected memory cell referring to program data to be written in an interfering cell configured to provide interference for the selected memory cell and programming the selected memory cell depending on the adjusted program-verify-voltage.

摘要翻译： 提供了一种非易失性存储器系统及其编程方法。 非易失性存储器系统的编程方法包括：参考要写入被配置为为所选存储器单元提供干扰的干扰单元的程序数据来调整所选存储器单元的编程验证电压，并根据 调整后的程序验证电压。

公开(公告)号：US09564237B2

公开(公告)日：2017-02-07

申请号：US14946848

申请日：2015-11-20

申请人： Changhyun Lee ,  Jungdal Choi ,  Byeong-In Choe

发明人： Changhyun Lee ,  Jungdal Choi ,  Byeong-In Choe

IPC分类号： G11C16/04 ,  G11C16/26 ,  G11C16/30 ,  G11C8/10 ,  G11C11/56 ,  G11C16/10 ,  G11C16/34 ,  G11C29/00

CPC分类号： G11C16/26 ,  G11C8/10 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/3418 ,  G11C16/3436 ,  G11C16/3454 ,  G11C16/3459 ,  G11C29/00

摘要： A nonvolatile memory device has improved reliability by compensating a threshold voltage of a flash memory cell. A nonvolatile memory device includes a memory cell array and a voltage generator for supplying a select read voltage to a select word line and an unselect read voltage to unselected word lines when a read operation is performed, and supplying a verify voltage to a select word line and the unselect read voltage to unselected word lines when a program operation is performed. The voltage generator supplies a first unselect read voltage to at least one between an upper word line and a lower word line adjacent to the select word line when the program operation is performed, and supplies a second unselected read voltage to at least one between the upper word line and the lower word line adjacent to the select word line when the read operation is performed.

摘要翻译： 非易失性存储器件通过补偿闪存单元的阈值电压而提高了可靠性。 非易失性存储器件包括：存储单元阵列和电压发生器，用于在执行读取操作时将选择读取电压提供给选择字线，并将未选择读取电压提供给未选择的字线;以及将验证电压提供给选择字线 以及当执行编程操作时，对未选字线的取消选择读取电压。 电压发生器在执行编程操作时将第一未读选择电压提供给与选择字线相邻的上字线和下字线之间的至少一个，并且将第二未选择读电压提供给上 当执行读操作时，字线和与选择字线相邻的下字线。

公开(公告)号：US09536895B2

公开(公告)日：2017-01-03

申请号：US14657849

申请日：2015-03-13

申请人： Changhyun Lee ,  Chanjin Park ,  Byoungkeun Son ,  Sung-Il Chang

发明人： Changhyun Lee ,  Chanjin Park ,  Byoungkeun Son ,  Sung-Il Chang

IPC分类号： H01L27/115

CPC分类号： H01L27/11582 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/11578 ,  H01L29/0649 ,  H01L29/7926

摘要： A three-dimensional semiconductor device includes an upper structure on a lower structure, the upper structure including conductive patterns, a semiconductor pattern connected to the lower structure through the upper structure, and an insulating spacer between the semiconductor pattern and the upper structure, a bottom surface of the insulating spacer being positioned at a vertical level equivalent to or higher than an uppermost surface of the lower structure.

摘要翻译： 三维半导体器件包括下结构的上结构，上结构包括导电图案，通过上结构连接到下结构的半导体图案，以及半导体图案和上结构之间的绝缘间隔物，底部 绝缘间隔物的表面位于等于或高于下部结构的最上表面的垂直水平。

公开(公告)号：US20160078955A1

公开(公告)日：2016-03-17

申请号：US14946848

申请日：2015-11-20

申请人： Changhyun Lee ,  Jungdal Choi ,  Byeong-ln Choe

发明人： Changhyun Lee ,  Jungdal Choi ,  Byeong-ln Choe

IPC分类号： G11C16/26 ,  G11C16/34 ,  G11C16/10

CPC分类号： G11C16/26 ,  G11C8/10 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/3418 ,  G11C16/3436 ,  G11C16/3454 ,  G11C16/3459 ,  G11C29/00

摘要： A nonvolatile memory device has improved reliability by compensating a threshold voltage of a flash memory cell. A nonvolatile memory device includes a memory cell array and a voltage generator for supplying a select read voltage to a select word line and an unselect read voltage to unselected word lines when a read operation is performed, and supplying a verify voltage to a select word line and the unselect read voltage to unselected word lines when a program operation is performed. The voltage generator supplies a first unselect read voltage to at least one between an upper word line and a lower word line adjacent to the select word line when the program operation is performed, and supplies a second unselected read voltage to at least one between the upper word line and the lower word line adjacent to the select word line when the read operation is performed.

摘要翻译： 非易失性存储器件通过补偿闪存单元的阈值电压而提高了可靠性。 非易失性存储器件包括：存储单元阵列和电压发生器，用于在执行读取操作时将选择读取电压提供给选择字线，并将未选择读取电压提供给未选择的字线;以及将验证电压提供给选择字线 以及当执行编程操作时，对未选字线的取消选择读取电压。 电压发生器在执行编程操作时将第一未读选择电压提供给与选择字线相邻的上字线和下字线之间的至少一个，并且将第二未选择读电压提供给上 当执行读操作时，字线和与选择字线相邻的下字线。

公开(公告)号：US08643080B2

公开(公告)日：2014-02-04

申请号：US13217416

申请日：2011-08-25

申请人： Changhyun Lee ,  Byoungkeun Son ,  Youngwoo Park

发明人： Changhyun Lee ,  Byoungkeun Son ,  Youngwoo Park

IPC分类号： H01L29/788 ,  H01L29/792 ,  H01L21/06 ,  H01L21/336

CPC分类号： H01L27/11578 ,  H01L27/11551 ,  H01L27/11556 ,  H01L29/7889 ,  H01L29/7926

摘要： Provided are three-dimensional semiconductor devices. The devices may include gap-fill insulating patterns configured to upwardly extend from a substrate and an electrode structure defined by sidewalls of the gap-fill insulating patterns. Vertical structures may be provided between adjacent ones of the gap-fill insulating patterns to penetrate the electrode structure, and the vertical structures may include first and second rows of the vertical structures. A separation pattern may be provided between the first and second rows of vertical structures and include a separation semiconductor layer. The separation pattern extends along a direction parallel to the first and second rows of vertical structures.

摘要翻译： 提供三维半导体器件。 这些装置可以包括配置成从基板向上延伸的间隙填充绝缘图案和由间隙填充绝缘图案的侧壁限定的电极结构。 可以在相邻的间隙填充绝缘图案之间提供垂直结构以穿透电极结构，并且垂直结构可以包括垂直结构的第一行和第二行。 可以在第一和第二排垂直结构之间提供分离图案，并且包括分离半导体层。 分离图案沿着平行于第一和第二排垂直结构的方向延伸。