公开(公告)号：US20050251599A1

公开(公告)日：2005-11-10

申请号：US10832606

申请日：2004-04-27

Applicant: Herbert Hum ,  Aaron Spink ,  Robert Blankenship

Inventor： Herbert Hum ,  Aaron Spink ,  Robert Blankenship

IPC: G06F13/00 ,  G06F15/173

CPC classification number: G06F15/17381

Abstract: In one embodiment of the present invention, a method includes identifying a transaction from a first processor to a second processor of a system with a transaction identifier. The transaction identifier may have a value that is less than or equal to a maximum number of outstanding transactions between the two processors. In such manner, a transaction field for the transaction identifier may be limited to n bits, where the maximum number of outstanding transactions is less than or equal to 2n. In various embodiments, such a transaction identifier combined with a source identifier and a home node identifier may form a globally unique transaction identifier.

Abstract translation: 在本发明的一个实施例中，一种方法包括从具有事务标识符的系统的第一处理器识别到第二处理器的事务。 事务标识符可以具有小于或等于两个处理器之间未完成事务的最大数量的值。 以这种方式，用于交易标识符的交易字段可以被限制为n位，其中未完成交易的最大数量小于或等于2。 在各种实施例中，与源标识符和家庭节点标识符组合的这种事务标识符可以形成全局唯一的事务标识符。

公开(公告)号：US09311085B2

公开(公告)日：2016-04-12

申请号：US11967230

申请日：2007-12-30

Applicant: Tingting Sha ,  Chris Wilkerson ,  Herbert Hum ,  Alaa R. Alameldeen

Inventor： Tingting Sha ,  Chris Wilkerson ,  Herbert Hum ,  Alaa R. Alameldeen

IPC: G06F9/312 ,  G06F9/30 ,  G06F9/45 ,  G06F9/38

CPC classification number: G06F9/30043 ,  G06F8/41 ,  G06F8/4442 ,  G06F9/30047 ,  G06F9/30185 ,  G06F9/3826 ,  G06F9/3891

Abstract: A method and apparatus for handling low power and high performance loads is herein described. Software, such as a compiler, is utilized to identify producer loads, consumer reuse loads, and consumer forwarded loads. Based on the identification by software, hardware is able to direct performance of the load directly to a load value buffer, a store buffer, or a data cache. As a result, accesses to cache are reduced, through direct loading from load and store buffers, without sacrificing load performance.

Abstract translation: 这里描述了用于处理低功率和高性能负载的方法和装置。 使用诸如编译器的软件来识别生产者负载，消费者重用负载和消费者转发的负载。 基于软件识别，硬件能够将负载的性能直接引导到负载值缓冲器，存储缓冲器或数据高速缓存。 因此，通过从加载和存储缓冲区直接加载，可以减少对缓存的访问，而不会牺牲负载性能。

公开(公告)号：US20130314425A1

公开(公告)日：2013-11-28

申请号：US13954979

申请日：2013-07-31

Applicant: Herbert Hum ,  Eric Sprangle ,  Doug Carmean ,  Rajesh Kumar

Inventor： Herbert Hum ,  Eric Sprangle ,  Doug Carmean ,  Rajesh Kumar

IPC: G06T1/20

CPC classification number: G06F1/3293 ,  G06F1/206 ,  G06F1/3203 ,  G06F1/3206 ,  G06F1/3228 ,  G06F1/324 ,  G06F1/3287 ,  G06F1/3296 ,  G06F9/3869 ,  G06F9/461 ,  G06F9/5088 ,  G06F9/5094 ,  G06F12/0875 ,  G06F13/24 ,  G06F2209/5017 ,  G06F2212/452 ,  G06T1/20 ,  Y02B70/10 ,  Y02B70/1425 ,  Y02B70/30 ,  Y02B70/32 ,  Y02D10/122 ,  Y02D10/126 ,  Y02D10/172 ,  Y02D50/20

Abstract: Techniques to control power and processing among a plurality of asymmetric cores. In one embodiment, one or more asymmetric cores are power managed to migrate processes or threads among a plurality of cores according to the performance and power needs of the system

Abstract translation: 控制多个不对称核心之间的功率和处理的技术。 在一个实施例中，根据系统的性能和功率需求，一个或多个非对称核被功率管理以在多个核之间迁移进程或线程

公开(公告)号：US08099587B2

公开(公告)日：2012-01-17

申请号：US11186240

申请日：2005-07-20

Applicant: Youfeng Wu ,  Sangwook Kim ,  Mauricio Breternitz, Jr. ,  Herbert Hum

Inventor： Youfeng Wu ,  Sangwook Kim ,  Mauricio Breternitz, Jr. ,  Herbert Hum

IPC: G06F9/00

CPC classification number: G06F12/06 ,  G06F8/4436 ,  G06F9/30178 ,  G06F2212/401

Abstract: An arrangement is provided for compressing microcode ROM (“uROM”) in a processor and for efficiently accessing a compressed “uROM”. A clustering-based approach may be used to effectively compress a uROM. The approach groups similar columns of microcode into different clusters and identifies unique patterns within each cluster. Only unique patterns identified in each cluster are stored in a pattern storage. Indices, which help map an address of a microcode word (“uOP”) to be fetched from a uROM to unique patterns required for the uOP, may be stored in an index storage. Typically it takes a longer time to fetch a uOP from a compressed uROM than from an uncompressed uROM. The compressed uROM may be so designed that the process of fetching a uOP (or uOPs) from a compressed uROM may be fully-pipelined to reduce the access latency.

Abstract translation: 提供了一种用于在处理器中压缩微代码ROM（“uROM”）并有效访问压缩的“uROM”的装置。 可以使用基于聚类的方法来有效地压缩uROM。 该方法将相似的微代码列组合成不同的集群，并识别每个集群内的唯一模式。 每个集群中唯一标识的模式都存储在模式存储中。 帮助将从uROM获取的微代码字（“uOP”）的地址映射到uOP所需的唯一模式的索引可以存储在索引存储器中。 通常，从压缩的uROM获取uop比从未压缩的uROM获取更长的时间。 压缩的uROM可以被设计成使得从压缩的uROM获取uop（或uop）的过程可以被完全流水线化以减少访问等待时间。

公开(公告)号：US20090222654A1

公开(公告)日：2009-09-03

申请号：US12220092

申请日：2008-07-22

Applicant: Herbert Hum ,  Eric Sprangle ,  Doug Carmean ,  Rajesh Kumar

Inventor： Herbert Hum ,  Eric Sprangle ,  Doug Carmean ,  Rajesh Kumar

IPC: G06F1/24 ,  G06F1/32 ,  G06F1/08

CPC classification number: G06F1/3293 ,  G06F1/206 ,  G06F1/3203 ,  G06F1/3206 ,  G06F1/3228 ,  G06F1/324 ,  G06F1/3287 ,  G06F1/3296 ,  G06F9/3869 ,  G06F9/461 ,  G06F9/5088 ,  G06F9/5094 ,  G06F12/0875 ,  G06F13/24 ,  G06F2209/5017 ,  G06F2212/452 ,  G06T1/20 ,  Y02B70/10 ,  Y02B70/1425 ,  Y02B70/30 ,  Y02B70/32 ,  Y02D10/122 ,  Y02D10/126 ,  Y02D10/172 ,  Y02D50/20

Abstract: Techniques to control power and processing among a plurality of asymmetric cores. In one embodiment, one or more asymmetric cores are power managed to migrate processes or threads among a plurality of cores according to the performance and power needs of the system.

Abstract translation: 控制多个不对称核心之间的功率和处理的技术。 在一个实施例中，根据系统的性能和功率需求，一个或多个非对称核被功率管理以在多个核之间迁移进程或线程。

公开(公告)号：US20080005482A1

公开(公告)日：2008-01-03

申请号：US11479179

申请日：2006-06-30

Applicant: Robert Beers ,  Herbert Hum

Inventor： Robert Beers ,  Herbert Hum

IPC: G06F13/28

CPC classification number: G06F12/0831 ,  G06F12/0813 ,  G06F12/0828

Abstract: A method for resolving data request conflicts in a cache coherency protocol for multiple caching agents using requester-generated data forwards. In one embodiment, a caching agent stores information used to auto-generate a forward of data received in response to a data request.

Abstract translation: 一种用于使用请求者生成的数据转发来解决多个缓存代理的高速缓存一致性协议中的数据请求冲突的方法。 在一个实施例中，高速缓存代理存储用于自动生成响应于数据请求而接收的数据的前向的信息。

公开(公告)号：US20070047584A1

公开(公告)日：2007-03-01

申请号：US11211063

申请日：2005-08-24

Applicant: Aaron Spink ,  Herbert Hum

Inventor： Aaron Spink ,  Herbert Hum

IPC: G01R31/08 ,  H04J3/24

CPC classification number: H04L49/9057 ,  H04L12/66 ,  H04L49/9021 ,  H04L49/9042 ,  H04L49/9094

Abstract: In one embodiment, the present invention includes a method for receiving a first portion of a first packet at a first agent and determining whether the first portion is an interleaved portion based on a value of an interleave indicator. The interleave indicator may be sent as part of the first portion. In such manner, interleaved packets may be sent within transmission of another packet, such as a lengthy data packet, providing improved processing capabilities. Other embodiments are described and claimed.

Abstract translation: 在一个实施例中，本发明包括一种用于在第一代理处接收第一分组的第一部分并基于交织指示符的值确定第一部分是交织部分的方法。 交错指示符可以作为第一部分的一部分发送。 以这种方式，交织的分组可以在另一个分组（例如冗长的数据分组）的传输内发送，从而提供改进的处理能力。 描述和要求保护其他实施例。

公开(公告)号：US20070002760A1

公开(公告)日：2007-01-04

申请号：US11173643

申请日：2005-06-30

Applicant: Keshavan Tiruvallur ,  David Poisner ,  Herbert Hum ,  Frank Binns ,  David Hill ,  Robert Greiner ,  Raymond Tetrick

Inventor： Keshavan Tiruvallur ,  David Poisner ,  Herbert Hum ,  Frank Binns ,  David Hill ,  Robert Greiner ,  Raymond Tetrick

IPC: H04J1/16

CPC classification number: G06F17/5068 ,  G06F17/5045

Abstract: Architectures and techniques that allow legacy pin functionality to be replaced with a “virtual wire” that may communicate information that would otherwise be communicated by a wired interface. A message may be passed between a system controller and a processor that includes a virtual wire value and a virtual wire change indicator. The virtual wire value may include a signal corresponding to one or more pins that have been eliminated from the physical interface and the virtual wire change value may include an indication of whether the virtual wire value has changed. The combination of the virtual wire value and the virtual wire change indicator may allow multiple physical pins to be replaced by message values.

Abstract translation: 允许传统引脚功能被替换为“虚拟线”的架构和技术，“虚拟线”可以传达否则将由有线接口传送的信息。 可以在系统控制器和包括虚拟线路值和虚拟换线指示器的处理器之间传递消息。 虚拟线值可以包括对应于已经从物理接口消除的一个或多个引脚的信号，并且虚拟线更改值可以包括虚拟线值是否已经改变的指示。 虚拟线路值和虚拟线路变化指示器的组合可以允许多个物理引脚被消息值替换。

公开(公告)号：US20050144388A1

公开(公告)日：2005-06-30

申请号：US10750715

申请日：2003-12-31

Applicant: Chris Newburn ,  Ram Huggahalli ,  Herbert Hum ,  Ali-Reza Adl-Tabatabai ,  Anwar Ghuloum

Inventor： Chris Newburn ,  Ram Huggahalli ,  Herbert Hum ,  Ali-Reza Adl-Tabatabai ,  Anwar Ghuloum

IPC: G06F12/08 ,  G06F12/00

CPC classification number: G06F12/0802 ,  G06F12/0886 ,  G06F2212/401

Abstract: A memory controller is described that comprises a compression map cache. The compression map cache is to store information that identifies a cache line's worth of information that has been compressed with another cache line's worth of information. A processor and a memory controller integrated on a same semiconductor die is also described. The memory controller comprises a compression map cache. The compression map cache is to store information that identifies a cache line's worth of information that has been compressed with another cache line's worth of information.

Abstract translation: 描述了包括压缩映射高速缓存的存储器控​​制器。 压缩映射缓存用于存储标识缓存行的信息值的信息，该信息已被另一个高速缓存行的信息压缩。 还描述了集成在同一半导体管芯上的处理器和存储器控制器。 存储器控制器包括压缩映射高速缓存。 压缩映射缓存用于存储标识缓存行的信息值的信息，该信息已被另一个高速缓存行的信息压缩。

公开(公告)号：US20050027963A1

公开(公告)日：2005-02-03

申请号：US10917449

申请日：2004-08-13

Applicant: Herbert Hum ,  Stephan Jourdan ,  Per Hammarlund

Inventor： Herbert Hum ,  Stephan Jourdan ,  Per Hammarlund

IPC: G06F12/10 ,  G06F12/08

CPC classification number: G06F12/1054 ,  G06F12/1063 ,  G06F12/109

Abstract: A system and method for reducing linear address aliasing is described. In one embodiment, a portion of a linear address is combined with a process identifier, e.g., a page directory base pointer to form an adjusted-linear address. The page directory base pointer is unique to a process and combining it with a portion of the linear address produces an adjusted-linear address that provides a high probability of no aliasing. A portion of the adjusted-linear address is used to search an adjusted-linear-addressed cache memory for a data block specified by the linear address. If the data block does not reside in the adjusted-linear-addressed cache memory, then a replacement policy selects one of the cache lines in the adjusted-linear-addressed cache memory and replaces the data block of the selected cache line with a data block located at a physical address produced from translating the linear address. The tag for the cache line selected is a portion of the adjusted linear address and the physical address produced from translating the linear address.

Abstract translation: 描述了用于减少线性地址混叠的系统和方法。 在一个实施例中，线性地址的一部分与进程标识符（例如，页目录基本指针）组合以形成调整后的线性地址。 页面目录基本指针对于进程是唯一的，并且将其与线性地址的一部分组合产生调整的线性地址，其提供没有别名的高概率。 调整后的线性地址的一部分用于搜索由线性地址指定的数据块的经调整的线性寻址高速缓冲存储器。 如果数据块不在调整后的线性寻址高速缓冲存储器中，则替换策略选择调整后的线性寻址高速缓存存储器中的一条高速缓存行，并用数据块替换所选择的高速缓存线的数据块 位于从翻译线性地址产生的物理地址。 所选择的高速缓存线的标签是调整后的线性地址的一部分和通过转换线性地址产生的物理地址。