公开(公告)号：US09805770B1

公开(公告)日：2017-10-31

申请号：US15217739

申请日：2016-07-22

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： Emmanuelle J. Merced Grafals ,  John Paul Strachan ,  Noraica Davila

IPC: G11C7/00 ,  G11C13/00 ,  G11C11/56 ,  H01L23/528

CPC classification number: G11C7/00 ,  G11C11/5614 ,  G11C13/0007 ,  G11C13/003 ,  G11C13/004 ,  G11C13/0064 ,  G11C13/0069 ,  G11C13/0097 ,  G11C2013/0066 ,  G11C2013/0071 ,  G11C2013/0076 ,  G11C2013/0083 ,  G11C2213/79 ,  H01L23/528

Abstract: A set procedure of a one transistor, one memristor memory elements may comprise determining a gate voltage for the transistor based on the desired target value. Increasing set pulses may be applied to memristor while the gate is held at the determined gate voltage.

公开(公告)号：US12242966B2

公开(公告)日：2025-03-04

申请号：US18528935

申请日：2023-12-05

Applicant: Hewlett Packard Enterprise Development LP

Inventor： Sai Rahul Chalamalasetti ,  Paolo Faraboschi ,  Martin Foltin ,  Catherine Graves ,  Dejan S. Milojicic ,  John Paul Strachan ,  Sergey Serebryakov

IPC: G11C7/00 ,  G06N3/08 ,  G11C13/00

Abstract: A crossbar array includes a number of memory elements. An analog-to-digital converter (ADC) is electronically coupled to the vector output register. A digital-to-analog converter (DAC) is electronically coupled to the vector input register. A processor is electronically coupled to the ADC and to the DAC. The processor may be configured to determine whether division of input vector data by output vector data from the crossbar array is within a threshold value, and if not within the threshold value, determine changed data values as between the output vector data and the input vector data, and write the changed data values to the memory elements of the crossbar array.

公开(公告)号：US20240112029A1

公开(公告)日：2024-04-04

申请号：US18528935

申请日：2023-12-05

Applicant: Hewlett Packard Enterprise Development LP

Inventor： Sai Rahul Chalamalasetti ,  Paolo Faraboschi ,  Martin Foltin ,  Catherine Graves ,  Dejan S. Milojicic ,  John Paul Strachan ,  Sergey Serebryakov

IPC: G06N3/08 ,  G11C13/00

CPC classification number: G06N3/08 ,  G11C13/0069 ,  G11C2213/77

Abstract: A crossbar array includes a number of memory elements. An analog-to-digital converter (ADC) is electronically coupled to the vector output register. A digital-to-analog converter (DAC) is electronically coupled to the vector input register. A processor is electronically coupled to the ADC and to the DAC. The processor may be configured to determine whether division of input vector data by output vector data from the crossbar array is within a threshold value, and if not within the threshold value, determine changed data values as between the output vector data and the input vector data, and write the changed data values to the memory elements of the crossbar array.

公开(公告)号：US20240111970A1

公开(公告)日：2024-04-04

申请号：US18528086

申请日：2023-12-04

Applicant: Hewlett Packard Enterprise Development LP

Inventor： John Paul Strachan ,  Dejan S. Milojicic ,  Martin Foltin ,  Sai Rahul Chalamalasetti ,  Amit S. Sharma

IPC: G06J1/00 ,  G06F17/16

CPC classification number: G06J1/00 ,  G06F17/16

Abstract: In some examples, a device includes a first processing core comprising a resistive memory array to perform an analog computation, and a digital processing core comprising a digital memory programmable with different values to perform different computations responsive to respective different conditions. The device further includes a controller to selectively apply input data to the first processing core and the digital processing core.

公开(公告)号：US11804859B2

公开(公告)日：2023-10-31

申请号：US17580146

申请日：2022-01-20

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： John Paul Strachan ,  Can Li ,  Catherine Graves

IPC: H03M13/00 ,  H03M13/15 ,  G11C13/00 ,  H03M13/11 ,  G11C27/00

CPC classification number: H03M13/6597 ,  G11C13/004 ,  H03M13/1575 ,  G11C13/0069 ,  G11C27/005 ,  H03M13/1177

Abstract: An analog error correction circuit is disclosed that implements an analog error correction code. The analog circuit includes a crossbar array of memristors or other non-volatile tunable resistive memory devices. The crossbar array includes a first crossbar array portion programmed with values of a target computation matrix and a second crossbar array portion programmed with values of an encoder matrix for correcting computation errors in the matrix multiplication of an input vector with the computation matrix. The first and second crossbar array portions share the same row lines and are connected to a third crossbar array portion that is programmed with values of a decoder matrix, thereby enabling single-cycle error detection. A computation error is detected based on output of the decoder matrix circuitry and a location of the error is determined via an inverse matrix multiplication operation whereby the decoder matrix output is fed back to the decoder matrix.

公开(公告)号：US11650751B2

公开(公告)日：2023-05-16

申请号：US16368981

申请日：2019-03-29

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： Suhas Kumar ,  Thomas Van Vaerenbergh ,  John Paul Strachan

IPC: G06F17/11 ,  G06N10/00 ,  G06F3/06

CPC classification number: G06F3/0655 ,  G06F3/0604 ,  G06F3/0679 ,  G06F17/11 ,  G06N10/00

Abstract: A method for determining a solution to a constrained optimization problem includes programming a weights matrix of a Hopfield network with a first encoded matrix representation of an initial constrained optimization problem. The method also includes employing the Hopfield network to determine a solution to the initial constrained optimization problem. Additionally, the method includes encoding a plurality of constrained optimization problems associated with a target constrained optimization problem into a plurality of encoded matrix representations each of which are a combination of the first and the second encoded matrix representations. The plurality of encoded matrix representations increases in convergence to the second encoded matrix representation of the target constrained optimization problem sequentially. The method further includes re-programming the weights matrix of the Hopfield network in an iterative manner with the plurality of encoded matrix representations.

公开(公告)号：US11551056B2

公开(公告)日：2023-01-10

申请号：US16261398

申请日：2019-01-29

Applicant: Hewlett Packard Enterprise Development LP

Inventor： John Paul Strachan ,  Suhas Kumar ,  Thomas Van Vaerenbergh

IPC: G06N3/04 ,  G06N3/08 ,  G06N3/063

Abstract: Staged neural networks and methods are described herein. In some embodiments, the methods may identify a plurality of second NP hard/complete problems that are similar to the first NP hard/complete problem and identify solutions to the second NP hard/complete problems. The methods may train a deep neural network with the second NP hard/complete problems and the solutions. The methods may provide the first NP hard/complete problem to the trained deep neural network to generate a preliminary solution to the first NP hard/complete problem and provide the preliminary solution to a recursive neural network configured to execute an energy minimization search. The recursive neural network may generate a final solution to the problem based on the preliminary solution.

公开(公告)号：US11355899B2

公开(公告)日：2022-06-07

申请号：US17004955

申请日：2020-08-27

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： Bassem Tossoun ,  Di Liang ,  John Paul Strachan

IPC: H01S5/026 ,  H01L45/00 ,  H01S5/042 ,  H01S5/0225 ,  H01S5/30 ,  H01S5/10

Abstract: An optical device includes a light-emitting device integrated with a memory device. The memory device include a first electrode and a second electrode, and the light-emitting device includes a third electrode and the second electrode. In such configuration, a first voltage between the second electrode and the third electrode causes the light-emitting device to emit light of a first wavelength, and a second voltage between the first electrode and the second electrode while the memory device is at OFF state causes the light-emitting device to emit light of a second wavelength shorter than the first wavelength or while the memory device is at ON state causes the light-emitting device to emit light of a third wavelength longer than the first wavelength.

公开(公告)号：US20210201136A1

公开(公告)日：2021-07-01

申请号：US17044633

申请日：2018-04-30

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： Sai Rahul Chalamalasetti ,  Paolo Faraboschi ,  Martin Foltin ,  Catherine Graves ,  Dejan S. Milojicic ,  John Paul Strachan ,  Sergey Serebryakov

IPC: G06N3/08 ,  G11C13/00

Abstract: A crossbar array includes a number of memory elements. An analog-to-digital converter (ADC) is electronically coupled to the vector output register. A digital-to-analog converter (DAC) is electronically coupled to the vector input register. A processor is electronically coupled to the ADC and to the DAC. The processor may be configured to determine whether division of input vector data by output vector data from the crossbar array is within a threshold value, and if not within the threshold value, determine changed data values as between the output vector data and the input vector data, and write the changed data values to the memory elements of the crossbar array.

公开(公告)号：US20200218967A1

公开(公告)日：2020-07-09

申请号：US16371230

申请日：2019-04-01

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： John Paul Strachan ,  Suhas Kumar

IPC: G06N3/063 ,  G06N3/04 ,  G06N3/08

Abstract: A hardware accelerator including a crossbar array programmed to calculate node values of a neural network, the crossbar array comprising a plurality of row lines, a plurality of column lines, and a memory cell coupled between each combination of one row line and one column line. Also, an energy storing element disposed in the crossbar array between each combination of one row line and one column line and a filter that receives information from the energy storing element and provides new information for each node of the neural network.