公开(公告)号：US20090096032A1

公开(公告)日：2009-04-16

申请号：US12093666

申请日：2006-10-18

申请人： Motofumi Saitoh ,  Hirohito Watanabe

发明人： Motofumi Saitoh ,  Hirohito Watanabe

IPC分类号： H01L27/092 ,  H01L21/8234

CPC分类号： H01L21/823842 ,  H01L21/28097 ,  H01L21/823835 ,  H01L21/823871 ,  H01L29/66545 ,  H01L29/6656 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device includes first and second active regions on a semiconductor substrate, separated by an element isolation region; a line-shaped electrode disposed from over the first to over the second active region via the element isolation region; first and second FETs including a gate insulating film on the first and second active regions, respectively, a gate electrode composed of the line-shaped electrode and a source/drain region. Parts of the line-shaped electrode over the first and second active regions are formed of different materials. The line-shaped electrode includes a diffusion restraining region having thickness in a direction perpendicular to the substrate thinner than that over the first and second active regions. The diffusion restraining region is over the element isolation region and spans the whole width of the line-shaped electrode in the gate length direction.

摘要翻译： 半导体器件包括半导体衬底上的第一和第二有源区，由元件隔离区隔开; 线状电极，其经由元件隔离区域从第一至第二有源区域上方设置; 第一和第二FET分别包括在第一和第二有源区上的栅极绝缘膜，由线状电极和源极/漏极区组成的栅电极。 第一和第二活性区域上的线状电极的部分由不同的材料形成。 线状电极包括扩散抑制区域，该扩散抑制区域在垂直于衬底的方向上的厚度小于第一和第二有源区域上的厚度。 扩散抑制区域在元件隔离区域的上方，并且跨越栅极长度方向的线状电极的整个宽度。

公开(公告)号：US20050253181A1

公开(公告)日：2005-11-17

申请号：US11129440

申请日：2005-05-16

申请人： Naohiko Kimizuka ,  Kiyotaka Imai ,  Yuri Masuoka ,  Toshiyuki Iwamoto ,  Motofumi Saitoh ,  Hirohito Watanabe ,  Masayuki Terai

发明人： Naohiko Kimizuka ,  Kiyotaka Imai ,  Yuri Masuoka ,  Toshiyuki Iwamoto ,  Motofumi Saitoh ,  Hirohito Watanabe ,  Masayuki Terai

IPC分类号： H01L27/092 ,  H01L21/8238 ,  H01L29/78 ,  H01L31/119

CPC分类号： H01L29/517 ,  H01L21/823857 ,  H01L29/4916 ,  H01L29/513 ,  H01L2924/0002 ,  H01L2924/00

摘要： The semiconductor device 100 comprises a silicon substrate 102, an N-type MOSFET 118 including a first high dielectric constant film 111 and a polycrystalline silicon film 114 formed on the silicon substrate 102, and a P-type MOSFET 120 including a second high dielectric constant film 112 and a polycrystalline silicon film 114 juxtaposed to N-type MOSFET 118 on the silicon substrate 102. The second high dielectric constant film 112 is formed to have the film thickness thinner than the film thickness of the first high dielectric constant film 111. The first high dielectric constant film 111 and the second high dielectric constant film 112 contains one or more element(s) selected from a group consisting of Hf and Zr.

摘要翻译： 半导体器件100包括硅衬底102，包括形成在硅衬底102上的第一高介电常数膜111和多晶硅膜114的N型MOSFET 118和包括第二高介电常数的P型MOSFET 120 膜112和与硅衬底102上的N型MOSFET 118并列的多晶硅膜114.第二高介电常数膜112形成为具有比第一高介电常数膜111的膜厚薄的膜厚度。 第一高介电常数膜111和第二高介电常数膜112包含从由Hf和Zr组成的组中选择的一种或多种元素。

公开(公告)号：US06853782B2

公开(公告)日：2005-02-08

申请号：US10194226

申请日：2002-07-15

申请人： Kazunaga Kobayashi ,  Masahiro Kusakari ,  Matsuhiro Miyamoto ,  Hirohito Watanabe ,  Keiji Ohashi

发明人： Kazunaga Kobayashi ,  Masahiro Kusakari ,  Matsuhiro Miyamoto ,  Hirohito Watanabe ,  Keiji Ohashi

IPC分类号： G02B6/44

CPC分类号： G02B6/4429 ,  G02B6/4403

摘要： An optical fiber drop cable includes an optical element portion having an optical fiber core wire and a pair of first tension members disposed parallel to the optical fiber core wire on both sides thereof in a sandwiching manner. The optical fiber core wire and the pair of first tension members are coated with a cable sheath. A long-scale cable support wire portion has a second tension member coated with a sheath. The optical element portion and the cable support wire portion are adhered parallel to each other. The first tension members are composed of a nonconductive material. A flexural rigidity of the optical element portion is in a range from 80 to 500 Nmm2.

摘要翻译： 光纤分路电缆包括具有光纤芯线的光学元件部分和以夹着方式平行于光纤芯线布置在其两侧的一对第一拉伸元件。 光纤芯线和一对第一张力构件涂覆有电缆护套。 长规格电缆支撑线部分具有涂覆有护套的第二张力构件。 光学元件部分和电缆支撑线部分彼此平行地粘合。 第一张力构件由非导电材料构成。 光学元件部的弯曲刚度在80〜500Nmm 2的范围内。

公开(公告)号：US06515322B1

公开(公告)日：2003-02-04

申请号：US08650948

申请日：1996-05-20

申请人： Hirohito Watanabe

发明人： Hirohito Watanabe

IPC分类号： H01L2976

CPC分类号： H01L29/78391

摘要： A nonvolatile semiconductor memory comprises a silicon substrate, a gate electrode formed through a gate insulator film on a principal surface of the semiconductor substrate, a pair of source/drain regions formed in a principal surface region of the semiconductor substrate to locate the gate electrode between the pair of source/drain regions. The gate insulator film is formed of a silicon oxide and/or silicon nitride film in contact with the principal surface of the semiconductor substrate, and a lead germanate film which is formed on the silicon oxide and/or silicon nitride film and which is a ferroelectric having a dielectric constant of not larger than 50.

摘要翻译： 非易失性半导体存储器包括硅衬底，通过半导体衬底的主表面上的栅绝缘膜形成的栅电极，形成在半导体衬底的主表面区域中的一对源/漏区，以将栅电极定位在 一对源极/漏极区域。 栅极绝缘膜由与半导体衬底的主表面接触的氧化硅和/或氮化硅膜形成，并且形成在氧化硅和/或氮化硅膜上并且是铁电体 介电常数不大于50。

公开(公告)号：US6033978A

公开(公告)日：2000-03-07

申请号：US754519

申请日：1996-11-21

申请人： Kunihiro Fujii ,  Hirohito Watanabe

发明人： Kunihiro Fujii ,  Hirohito Watanabe

IPC分类号： H01L21/28 ,  H01L21/285 ,  H01L21/336 ,  H01L21/768 ,  H01L21/8238 ,  H01L21/4763 ,  H01L21/3205 ,  H01L21/44

CPC分类号： H01L21/28518 ,  H01L21/823814 ,  H01L21/823835 ,  H01L29/665

摘要： Amorphous silicon layers are formed on an n-type single-crystal/poly-crystal layer and a p-type single-crystal/poly-crystal layer, and titanium is sputtered on the amorphous silicon layers; although the n-type dopant impurity are piled on the n-type single-crystal/poly-crystal layers, the amorphous silicon layers takes the piles of n-type dopant impurity thereinto, and promote the silicidation of the titanium layer.

摘要翻译： 在n型单晶/多晶层和p型单晶/多晶层上形成无定形硅层，并将钛溅射在非晶硅层上; 虽然n型掺杂剂杂质堆积在n型单晶/多晶层上，但是非晶硅层将n型掺杂剂杂质堆入其中，促进了钛层的硅化。

公开(公告)号：US5863602A

公开(公告)日：1999-01-26

申请号：US862398

申请日：1997-05-23

申请人： Hirohito Watanabe ,  Toshiyuki Hirota ,  Takashi Ogawa

发明人： Hirohito Watanabe ,  Toshiyuki Hirota ,  Takashi Ogawa

IPC分类号： H01L21/205 ,  B08B17/00 ,  C23C16/44 ,  H01L21/8242 ,  H01L27/108 ,  C23C16/24

CPC分类号： C23C16/4404 ,  B08B17/00

摘要： Before an HSG-Si film is formed, silicon films are pre-coated on the inner wall of a reaction chamber (12) for forming the HSG-Si film on a wafer (14) and in a boat (25) which is used for accommodate and support the wafer (14) in the reaction chamber (12), and then the wafer (14) is fed into the pre-coated reaction chamber (12) to form the HSG-Si film in the state that impurities on the wafer (14) have been removed. By pre-coating the silicon films, the impurities such as water, oxygen, hydrocarbon and organic materials can be removed, and a surface area increase rate of the HSG-Si film formed on the wafer (14) can be improved.

摘要翻译： 在形成HSG-Si膜之前，将硅膜预先涂覆在反应室（12）的内壁上，用于在晶片（14）上形成HSG-Si膜，并在船（25）中用于 容纳并支撑反应室（12）中的晶片（14），然后将晶片（14）进料到预涂反应室（12）中以在晶片上的杂质的状态下形成HSG-Si膜 （14）已被删除。 通过预涂硅膜，可以除去诸如水，氧，烃和有机材料的杂质，并且可以提高在晶片（14）上形成的HSG-Si膜的表面积增加率。

公开(公告)号：US5723379A

公开(公告)日：1998-03-03

申请号：US177995

申请日：1994-01-06

申请人： Hirohito Watanabe ,  Toru Tatsumi

发明人： Hirohito Watanabe ,  Toru Tatsumi

IPC分类号： H01L21/02 ,  H01L27/108 ,  H01L29/92 ,  H01L21/205

CPC分类号： H01L27/10817 ,  H01L28/84 ,  H01L28/82 ,  H01L28/90 ,  Y10S438/964

摘要： A method for fabricating a polycrystalline silicon having a roughed surface, which is useful for a capacitor electrode is disclosed. The method is featured by depositing a polycrystalline silicon layer in such a manner that grains of silicon are caused at the surface of the polycrystalline silicon layer. The polycrystalline silicon layer thus obtained has a large effective area and is suitable for a capacitor electrode because of its increased effective surface area.

摘要翻译： 公开了一种用于制造具有粗糙表面的多晶硅的方法，其用于电容器电极。 该方法的特征在于以多晶硅层的表面上形成硅晶粒的方式沉积多晶硅层。 由此获得的多晶硅层的有效面积大，适合于电容电极，因为其有效表面积增加。

公开(公告)号：US5623243A

公开(公告)日：1997-04-22

申请号：US447678

申请日：1995-05-23

申请人： Hirohito Watanabe ,  Toru Tatsumi

发明人： Hirohito Watanabe ,  Toru Tatsumi

IPC分类号： H01L21/02 ,  H01L27/108 ,  H01L29/68 ,  H01L24/04

CPC分类号： H01L28/84 ,  H01L27/10817 ,  H01L28/82 ,  H01L28/90 ,  Y10S438/964

摘要： A semiconductor device having a roughed surface, which is useful for a capacitor electrode is disclosed. The device is featured by depositing a polycrystalline silicon layer in such a manner that polycrystalline grains having a hemispherical like shape or a mushroom like shape are caused at the surface of the polycrystalline silicon layer. A dielectric is formed on the polycrystalline layer having an uneven surface. A conductive layer is formed on the dielectric layer. The semiconductor device thus obtained has a large effective surface area and is suitable for a capacitor electrode because of its increased effective surface area from the hemispherical like shaped or mushroom like shaped polycrystalline grains.

摘要翻译： 公开了一种具有粗糙表面的半导体器件，其可用于电容器电极。 该器件的特征在于以多晶硅层的表面形成具有半球形或蘑菇形状的多晶晶粒的方式沉积多晶硅层。 在具有不平坦表面的多晶层上形成电介质。 在电介质层上形成导电层。 这样获得的半导体器件具有大的有效表面积，并且适合于电容器电极，因为其从半球形状或蘑菇形状的多晶晶粒增加了有效表面积。

公开(公告)号：US08809687B2

公开(公告)日：2014-08-19

申请号：US13077304

申请日：2011-03-31

申请人： Hirohito Watanabe

发明人： Hirohito Watanabe

IPC分类号： H05K1/00 ,  H05K1/03 ,  H05K9/00

CPC分类号： H05K1/028 ,  H05K1/0218 ,  H05K3/1216 ,  H05K2201/0373

摘要： [Object]To provide a flexible printed board improved in bendability.[Means for solving]The flexible printed board 2 comprises: an insulating substrate 21; a circuit wiring 22 laid on the insulating substrate 21; a circuit protection layer 23 laid on the circuit wiring 22; a shield conductive layer 24 laid on the circuit protection layer 23; and a shield insulating layer 25 laid on the shield conductive layer 24, and is characterized by meeting the following Expression (1). 0.75≦E2/E1≦1.29  Expression (1) Note that E1 denotes the tensile elastic modulus of the shield conductive layer 24 and E2 denotes the tensile elastic modulus of the shield insulating layer 25.

摘要翻译： 提供改善弯曲性的柔性印刷电路板。 [解决方案]柔性印刷电路板2包括：绝缘基板21; 布置在绝缘基板21上的电路布线22; 布置在电路布线22上的电路保护层23; 布置在电路保护层23上的屏蔽导电层24; 以及敷设在屏蔽导电层24上的屏蔽绝缘层25，其特征在于满足下述式（1）。 0.75＆nlE; E2 / E1＆nlE; 1.29表达式（1）注意，E1表示屏蔽导电层24的拉伸弹性模量，E2表示屏蔽绝缘层25的拉伸弹性模量。

公开(公告)号：US08574449B2

公开(公告)日：2013-11-05

申请号：US13462399

申请日：2012-05-02

申请人： Hirohito Watanabe ,  Taiji Ogawa ,  Eriko Tomonaga

发明人： Hirohito Watanabe ,  Taiji Ogawa ,  Takaomi Tomonaga

IPC分类号： B44C1/22

CPC分类号： H05K1/0269 ,  H05K3/06 ,  H05K2201/09781 ,  H05K2203/1545 ,  H05K2203/163

摘要： Quickly making changes to etching conditions suppresses the production yield of printed wiring boards from being deteriorated. Disclosed is a method comprising: an etching step that comprises: preparing a conductor-clad base material continuous in a certain direction, the conductor-clad base material (1) having an insulating layer and one or more conductive layers formed on main surfaces of the insulating layer; and subjecting a predetermined region of a conductor layer of one main surface of the conductor-clad base material (1) to an etching process thereby to form a wiring pattern (1a) to be of a product and an inspection pattern (1b) to be used for inspection; a measuring step that measures a line width of the inspection pattern after the etching step; and a control step that controls an etching condition in the etching step based on the measured line width.

摘要翻译： 迅速改变蚀刻条件抑制了印刷电路板的生产成本的恶化。 公开了一种方法，包括：蚀刻步骤，包括：制备在一定方向上连续的导体包覆基材，所述导体包覆基材（1）具有绝缘层和形成在所述导体包覆基材的主表面上的一个或多个导电层 绝缘层; 并且对导体包覆基材（1）的一个主表面的导体层的预定区域进行蚀刻处理，从而形成作为产品的布线图案（1a）和检查图案（1b） 用于检验; 测量步骤，其测量所述蚀刻步骤之后的所述检查图案的线宽; 以及控制步骤，其基于所测量的线宽来控制蚀刻步骤中的蚀刻条件。