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公开(公告)号：US06640194B2
公开(公告)日：2003-10-28
申请号：US10001649
申请日：2001-10-31
申请人： James M. Little , Hiroshi Takatori , Scott Chiu
发明人： James M. Little , Hiroshi Takatori , Scott Chiu
IPC分类号： G01R1300
摘要： A frequency detector includes a slicer to receive and slice a phase error against a compare threshold value. The slicer generates a symbol based on the phase error sliced against the compare threshold value. A symbol counter is provided to increment a symbol count if the symbol generated is the same as a last symbol. A logic circuit compares the symbol count with a symbol count limit if the symbol is different from the last symbol. The logic circuit increments a high counter and clears a low counter if the symbol count is less than the symbol count limit. The logic circuit increments the low counter and clears the high counter if the symbol count is greater than the symbol count limit. A combinational logic circuit is provided to generate a high frequency jitter true signal or a high frequency jitter false signal based on at least one of the symbol count, the high counter, and the low counter.
摘要翻译： 频率检测器包括限幅器，用于根据比较阈值接收和切片相位误差。 限幅器基于相对于比较阈值切片的相位误差产生符号。 如果产生的符号与最后一个符号相同，则提供符号计数器来增加符号计数。 如果符号与最后一个符号不同，则逻辑电路将符号计数与符号计数限制进行比较。 如果符号计数小于符号计数限制，逻辑电路会增加一个高计数器并清除一个低计数器。 如果符号数大于符号计数限制，逻辑电路会递增低计数器并清除高计数器。 提供组合逻辑电路，用于基于符号计数，高计数器和低计数器中的至少一个产生高频抖动真实信号或高频抖动假信号。
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公开(公告)号：US06249557B1
公开(公告)日：2001-06-19
申请号：US09033769
申请日：1998-03-03
IPC分类号： H04L700
CPC分类号： H04L7/0058 , H04L7/0062 , H04L7/0083
摘要： A timing recovery circuit is disclosed that prevents phase error over-compensation. The timing recovery circuit includes a phase scanner for determining when phase error over-compensation has occurred and generating a signal for preventing dual phase compensation in response thereto thereby providing an accurate recovered clock signal. The timing recovery circuit also includes a feed-forward equalizer having a plurality of taps providing coefficients for filtering and adapting the input timing recovery circuit to an input signal. The phase scanner compares the tap coefficients to generate signal for preventing phase over-compensation by the feed-forward equalizer. A phase detector is provided for sampling coefficients from the feed-forward equalizer, error signals and output data and generating a phase signal used to generating the recovered clock signal. The signal for preventing phase over-compensation is mixed with the phase signal to generate the recovered clock signal.
摘要翻译： 公开了一种防止相位误差过度补偿的定时恢复电路。 定时恢复电路包括用于确定何时发生相位误差过补偿的相位扫描器，并且响应于此产生用于防止双相补偿的信号，从而提供精确的恢复时钟信号。 定时恢复电路还包括具有多个抽头的前馈均衡器，其提供用于滤波和适配输入定时恢复电路到输入信号的系数。 相位扫描器比较抽头系数以产生用于防止前馈均衡器的相位过补偿的信号。 提供相位检测器用于从前馈均衡器，误差信号和输出数据中采样系数，并产生用于产生恢复的时钟信号的相位信号。 用于防止相位过度补偿的信号与相位信号混合以产生恢复的时钟信号。
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公开(公告)号：US5581585A
公开(公告)日：1996-12-03
申请号：US327184
申请日：1994-10-21
CPC分类号： H04L25/03057 , H04L7/0058 , H04L7/0062 , H04L7/0083
摘要： A timing recovery apparatus for recovering the timing from sparse timing information in multi-level or partial response codes. The timing recovery apparatus includes a switch for sampling an incoming line code signal according to a selectable sample rate, a feed forward equalizer for filtering the sampled signal, a decision feedback equalizer for cancelling intersymbol interference in the filtered signal and for recovering the timing in the sampled signal. The timing recovery circuit creates a phase correction signal in response to a signal received from the feed forward equalizer and thereby control the sample rate of the sample switch so that the signal-to-noise ratio at the node before the decision is maximized. The voltage controlled crystal oscillator may be controlled within a certain frequency range by using a second phase detector which compares the phase of the signal controlling the sampling of the incoming line code with a reference clock.
摘要翻译： 一种定时恢复装置，用于从多级或部分响应码中的稀疏定时信息中恢复定时。 定时恢复装置包括用于根据可选采样率对输入线路码信号进行采样的开关，用于滤波采样信号的前馈均衡器，用于消除滤波信号中的码间干扰的判决反馈均衡器，以及用于恢复滤波信号中的定时 采样信号。 定时恢复电路响应于从前馈均衡器接收的信号创建相位校正信号，从而控制采样开关的采样率，使得决定之前的节点处的信噪比最大化。 通过使用第二相位检测器将压控晶体振荡器控制在一定频率范围内，该第二相位检测器将控制输入线路码的采样的信号的相位与参考时钟进行比较。
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公开(公告)号：US5181228A
公开(公告)日：1993-01-19
申请号：US596220
申请日：1990-10-12
申请人： Hiroshi Takatori
发明人： Hiroshi Takatori
摘要： A phase equalizer in the receiver portion of a bi-directional communication system is disclosed equalizer for reducing precursor intersymbol interference without any substantial degradation in signal to noise ratio. The phase equalizer is implemented as a switched capacitor filter having a clock (switch) rate at least four times the data baud rate and a z-transfer function T(z) of a form: ##EQU1## wherein G, A, and B are fixed but adjustable coefficients.
摘要翻译： 公开了双向通信系统的接收机部分中的相位均衡器，用于减少前置码间干扰，而信噪比没有任何明显的降低。 相位均衡器被实现为具有至少四倍于数据波特率的时钟（开关）速率和以下形式的z传递函数T（z）的开关电容滤波器：其中G，A和B是 固定但可调系数。
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公开(公告)号：US4833691A
公开(公告)日：1989-05-23
申请号：US149021
申请日：1988-01-27
CPC分类号： H04L25/03025 , H03H19/004 , H04L25/03057
摘要： A line equalizer for eliminating a precursor interference component and postcursor interference components from a pulse signal inputted from a transmission line. A precursor equalizer takes a sum of a signal derived from the input pulse signal retarded by a fundamental period and a signal derived from the input pulse signal multiplied by a coefficient a. A decision circuit decides the threshold level of an output pulse signal from the precursor equalizer to output a predetermined signal. A controller controls the coefficient a of the precursor equalizer on the basis of the signal from the decision circuit, etc.
摘要翻译： 一种线均衡器，用于消除从传输线输入的脉冲信号的前驱干扰分量和后脉冲干扰分量。 前驱均衡器取从由基本周期延迟的输入脉冲信号和从输入脉冲信号导出的信号乘以系数a的信号的和。 决定电路决定来自前驱均衡器的输出脉冲信号的阈值电平，输出规定的信号。 控制器根据来自判定电路的信号等来控制前驱均衡器的系数a。
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公开(公告)号：US09435514B2
公开(公告)日：2016-09-06
申请号：US14347646
申请日：2012-09-10
申请人： Hiroshi Takatori , Masao Yamaguchi
发明人： Hiroshi Takatori , Masao Yamaguchi
CPC分类号： F21V13/02 , G02B6/003 , G02B6/0031 , G02B6/0053 , G02B6/0096 , G02F1/133602 , G09F13/04 , G09F13/0409 , G09F13/14 , G09F2013/049 , G09F2013/147
摘要： In a surface light source device (1), a positive reflective region (23) of a reflective member (20) that is disposed on the bottom surface (4) of a housing (2) reflects light output by a light emitting device (14) toward a direction away from the light emitting device (14). As a result, the brightness of the light in the proximity of the light emitting device (14) of the surface shaped illuminating light output by a light emitting surface member (3) can be suppressed, and the brightness of light of a central part (position furthest away from the light emitting device (14)) of the surface shaped illuminating light output by the light emitting surface member (3) can be increased.
摘要翻译： 在表面光源装置（1）中，设置在壳体（2）的底面（4）上的反射构件（20）的正反射区域（23）反射由发光装置（14）输出的光 ）朝向远离发光器件（14）的方向。 结果，可以抑制由发光面部件（3）输出的表面形状的照明光的发光器件（14）附近的光的亮度，并且可以抑制中心部分 可以增加由发光面构件（3）输出的表面形状的照明光的距离发光装置（14）最远的位置。
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公开(公告)号：US09065644B2
公开(公告)日：2015-06-23
申请号：US13525544
申请日：2012-06-18
申请人： Hiroshi Takatori
发明人： Hiroshi Takatori
CPC分类号： H04L5/143 , H04B1/0475 , H04B1/0483 , H04B1/38 , H04L5/14 , H04L5/1461 , H04L7/042 , H04L27/36 , H04L27/366 , H04L69/323 , H04W88/14
摘要： An integrated circuit (IC) for a backplane serializer/deserializer (SerDes) system, comprising a first transmitter configured to send first data at a data rate to a second receiver in a second IC, a first receiver configured to receive second data at the data rate from a second transmitter in the second IC, wherein each of a first link and a second link is to the first transmitter, the first receiver, the second transmitter, and the second receiver, and wherein both the first link and the second link combined are configured to transfer the first data from the first transmitter to the second receiver and transfer the second data from the second transmitter to the first receiver at the data rate.
摘要翻译： 一种用于背板串行器/解串器（SerDes）系统的集成电路（IC），包括：第一发射机，被配置为以第二IC将数据速率的第一数据发送到第二IC中的第二接收机;第一接收机，被配置为接收数据的第二数据 速率来自第二IC中的第二发射机，其中第一链路和第二链路中的每一个到第一发射机，第一接收机，第二发射机和第二接收机，并且其中第一链路和第二链路都被组合 被配置为将第一数据从第一发射机传送到第二接收机，并以数据速率将第二数据从第二发射机传送到第一接收机。
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公开(公告)号：US08929429B2
公开(公告)日：2015-01-06
申请号：US12905912
申请日：2010-10-15
CPC分类号： H04L25/03038 , H03H11/26 , H03H11/46 , H03H15/02 , H03H21/0001 , H04B3/32 , H04L1/0047 , H04L25/03057 , H04L25/03133 , H04L25/03343 , H04L2025/03477 , H04L2025/0349 , H04L2025/03503 , H04L2025/03598
摘要： According to an embodiment of the disclosure, a communication transmitter and receiver include an adaptive filter and a decision feedback equalizer as well as cross-talk cancellers. The adaptive filter is configured to receive an input signal and includes a continuous analog delay circuit with a plurality of Padé-based delay elements.
摘要翻译： 根据本公开的实施例，通信发射机和接收机包括自适应滤波器和判决反馈均衡器以及串扰消除器。 自适应滤波器被配置为接收输入信号并且包括具有多个基于Padé的延迟元件的连续模拟延迟电路。
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29.发明申请公开(公告)号：US20130044496A1
公开(公告)日：2013-02-21
申请号：US13637190
申请日：2011-03-18
IPC分类号： F21V5/04
CPC分类号： G02B19/0071 , F21V5/04 , F21V9/08 , F21Y2115/10 , G02B19/0009 , G02B19/0014 , G02B19/0061 , H01L33/507 , H01L33/58
摘要： Provided are a lighting lens and an illumination apparatus including the same that can improve color rendering properties and prevent reductions in performance of a light flux controlling member and in illuminance on a surface to be illuminated when a pseudo-white LED is used. This lighting lens (1) includes a color adjustment unit (14) that contains a color adjusting material, is excited by light emitted from an LED (2) and emits light in a color different from the light-emitting color of the LED (2). The color adjustment unit (14) is disposed at a portion through which sub-rays other than main rays pass and not at a portion through which the main rays pass, the main rays being rays having a luminous intensity equal to or more than a predetermined percentage of the maximum luminous intensity.
摘要翻译： 本发明提供了一种照明透镜和包括该照明装置的照明装置，其可以在使用伪白色LED时能够提高显色性能并防止光束控制部件的性能和照明面上的照明。 该照明透镜（1）包括含有调色材料的颜色调整单元（14），被从LED（2）发出的光激发，并且发射与LED（2）的发光颜色不同的颜色 ）。 颜色调整单元（14）设置在除主光线以外的子光线通过的部分，而不是主射线通过的部分，主光线为具有等于或大于预定光线的发光强度的光线 百分比的最大发光强度。
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公开(公告)号：US20120327818A1
公开(公告)日：2012-12-27
申请号：US13525544
申请日：2012-06-18
申请人： Hiroshi Takatori
发明人： Hiroshi Takatori
CPC分类号： H04L5/143 , H04B1/0475 , H04B1/0483 , H04B1/38 , H04L5/14 , H04L5/1461 , H04L7/042 , H04L27/36 , H04L27/366 , H04L69/323 , H04W88/14
摘要： An integrated circuit (IC) for a backplane serializer/deserializer (SerDes) system, comprising a first transmitter configured to send first data at a data rate to a second receiver in a second IC, a first receiver configured to receive second data at the data rate from a second transmitter in the second IC, wherein each of a first link and a second link is to the first transmitter, the first receiver, the second transmitter, and the second receiver, and wherein both the first link and the second link combined are configured to transfer the first data from the first transmitter to the second receiver and transfer the second data from the second transmitter to the first receiver at the data rate.
摘要翻译： 一种用于背板串行器/解串器（SerDes）系统的集成电路（IC），包括：第一发射机，被配置为以第二IC将数据速率的第一数据发送到第二IC中的第二接收机;第一接收机，被配置为接收数据的第二数据 速率来自第二IC中的第二发射机，其中第一链路和第二链路中的每一个到第一发射机，第一接收机，第二发射机和第二接收机，并且其中第一链路和第二链路都被组合 被配置为将第一数据从第一发射机传送到第二接收机，并以数据速率将第二数据从第二发射机传送到第一接收机。
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