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121 条记录 (耗时 0.034 秒)

    Geometrical operation apparatus for performing high speed calculations in a three-dimensional computer graphic display system
    22.
    发明授权
    Geometrical operation apparatus for performing high speed calculations in a three-dimensional computer graphic display system 失效
    用于在三维计算机图形显示系统中执行高速计算的几何运算装置

    公开(公告)号：US6005590A

    公开(公告)日：1999-12-21

    申请号：US743178

    申请日：1996-11-05

    申请人： Hiroyasu Negishi ,  Masatoshi Kameyama ,  Yoshitsugu Inoue ,  Hiroyuki Kawai

    发明人： Hiroyasu Negishi ,  Masatoshi Kameyama ,  Yoshitsugu Inoue ,  Hiroyuki Kawai

    IPC分类号： G06F9/38 ,  G06F15/80 ,  G06T1/20 ,  G06T11/00 ,  G06T15/30 ,  G06F15/16

    CPC分类号： G06T1/20

    摘要： The apparatus comprises an input memory 102 for storing data necessary for geometrical operations, such as coordinate transformation, luminance calculation, and clipping operation of graphics; a global bus connected to the input memory; a plurality of floating process memories connected to the global bus, for receiving data necessary for geometrical operations; a sequencer for transmitting data necessary for geometrical operations, stored in the input memory, to the plurality of floating process memories; and a plurality of floating processing units each connected to a respective one of the plurality of floating process memories, for independently executing geometrical operations, using data transmitted from the floating process memories.

    摘要翻译： 该装置包括用于存储几何运算所必需的数据的输入存储器102，例如坐标变换，亮度计算和图形的剪切操作; 连接到输入存储器的全局总线; 连接到全局总线的多个浮动处理存储器，用于接收几何操作所需的数据; 定序器，用于将存储在输入存储器中的几何运算所需的数据发送到多个浮动处理存储器; 以及多个浮动处理单元，每个浮动处理单元都连接到多个浮动处理存储器中的相应一个浮动处理存储器，用于使用从浮动处理存储器发送的数据来独立地执行几何操作。

    Signal transmission circuit
    25.
    发明授权
    Signal transmission circuit 失效
    信号传输电路

    公开(公告)号：US4962343A

    公开(公告)日：1990-10-09

    申请号：US303797

    申请日：1989-01-27

    申请人： Shin-ichi Nakagawa ,  Hiroyuki Kawai

    发明人： Shin-ichi Nakagawa ,  Hiroyuki Kawai

    IPC分类号： G06F3/00 ,  H03K5/02 ,  H03K17/687 ,  H03K17/693 ,  H04L25/02

    CPC分类号： H03K17/6872 ,  H03K17/693 ,  H03K5/023 ,  H03K5/026

    摘要： A signal transmission circuit constructed such that, when a signal of one channel is transmitted in two-divided signal transmission lines, discharge switching elements on two precharged signal transmission lines are controlled by four switching elements (three P-channel MOS transistors and one N-channel MOS transistor). Therefore, when one signal transmission line is at a low level during a signal transmission period, the discharge switching elements of both the signal transmitting lines conduct, leading one signal transmission line to be discharged. This causes the low level signal to be transmitted to the other signal transmitting line.

    摘要翻译： 一种信号传输电路，其被构造成使得当在两分信号传输线中发送一个信道的信号时，两个预充电信号传输线上的放电开关元件由四个开关元件（三个P沟道MOS晶体管和一个N- 通道MOS晶体管）。 因此，在信号传输期间，当一个信号传输线处于低电平时，两个信号传输线的放电开关元件导通，导致一个信号传输线被放电。 这使得低电平信号被发送到另一个信号传输线。

    Variable delay circuit for delaying input data
    26.
    发明授权
    Variable delay circuit for delaying input data 失效
    用于延迟输入数据的可变延迟电路

    公开(公告)号：US4953128A

    公开(公告)日：1990-08-28

    申请号：US133790

    申请日：1987-12-16

    申请人： Hiroyuki Kawai ,  Masahiko Yoshimoto

    发明人： Hiroyuki Kawai ,  Masahiko Yoshimoto

    IPC分类号： G11C7/00 ,  G11C7/10 ,  G11C8/04 ,  G11C19/00 ,  H04N7/62

    CPC分类号： H04N21/4302 ,  G11C7/1006 ,  G11C8/04 ,  H04N21/242

    摘要： An address counter (2) counts the clock pulses sequentially to provide a count value as an address signal to a coincidence detecting circuit (3) and decoder (4). The coincidence detecting circuit (3) compares delay data applied from a delay data generating circuit (8) with the address signal and applies a reset signal to the address counter (2) when they coincide with each other. The address counter (2) repeats sequentially the above-mentioned operation in response to the reset signal after the count of address is reset to a predetermined value. The decoder (4) specifies a memory cell comprised in a memory device for performing a reading and writing operation in response to the address signal. The data output circuit (6) and the data input circuit (5) perform the reading and writing operation sequentially to the specified memory cell in response to the control signal outputted from the control circuit (7). As a result, the input data previously written is read and outputted with a delay. Therefore, a delayed input data can be obtained as an output data.

    摘要翻译： 地址计数器（2）对时钟脉冲进行顺序计数，以向计数器（3）和解码器（4）提供作为地址信号的计数值。 比较从延迟数据产生电路（8）施加的延迟数据与地址信号，并将复位信号与地址计数器（2）相互重合的同时检测电路（3）进行比较。 地址计数器（2）在将地址计数复位到预定值之后，响应于复位信号顺序重复上述操作。 解码器（4）指定包含在存储器件中的存储器单元，用于响应于地址信号执行读和写操作。 数据输出电路（6）和数据输入电路（5）响应于从控制电路（7）输出的控制信号，顺序地向指定的存储单元执行读和写操作。 结果，预先写入的输入数据被延迟地读出并输出。 因此，可以获得延迟的输入数据作为输出数据。

    Clock generator which generates a non-overlap clock having fixed pulse width and changeable frequency
    28.
    发明授权
    Clock generator which generates a non-overlap clock having fixed pulse width and changeable frequency 失效
    时钟发生器，其产生具有固定脉冲宽度和可变频率的非重叠时钟

    公开(公告)号：US4877974A

    公开(公告)日：1989-10-31

    申请号：US189885

    申请日：1988-05-03

    申请人： Hiroyuki Kawai ,  Shinichi Nakagawa

    发明人： Hiroyuki Kawai ,  Shinichi Nakagawa

    IPC分类号： G06F1/06 ,  H03K5/15

    CPC分类号： H03K5/1502 ,  H03K5/15033

    摘要： A clock generator which is cascade connected a plurality of single-phase pulse generator circuits including RS flip-flops and delay circuits for defining the pulse width of one output at the RS flip-flop through gates controlling propagation of the other output of the RS flip-flop, so that the final clock frequency is variable by switching control of each gate, whereby a pulse width of each single-phase clock is defined by a delay duration of a delay circuit, thereby not depending on wave forms of the external clock and also the gates connected between the respective single-phase pulse generating circuits are switching-controlled to enable the frequency of the output clock to be variable.

    摘要翻译： 串联连接多个单相脉冲发生器电路的时钟发生器，包括RS触发器和延迟电路，用于通过控制RS翻转的另一个输出的门限定RS触发器上的一个输出的脉冲宽度 使得最终时钟频率可通过切换每个门的控制而变化，由此每个单相时钟的脉冲宽度由延迟电路的延迟持续时间定义，从而不依赖于外部时钟的波形， 连接在各个单相脉冲发生电路之间的门也是开关控制的，以使输出时钟的频率可变。

    Image forming apparatus
    30.
    发明授权
    Image forming apparatus 有权
    图像形成装置

    公开(公告)号：US08294950B2

    公开(公告)日：2012-10-23

    申请号：US12545603

    申请日：2009-08-21

    申请人： Seiji Shiraki ,  Takaya Nagasaki ,  Hiroyuki Kawai ,  Yasuo Komatsu ,  Kiyoshi Une ,  Takumi Nishikata

    发明人： Seiji Shiraki ,  Takaya Nagasaki ,  Hiroyuki Kawai ,  Yasuo Komatsu ,  Kiyoshi Une ,  Takumi Nishikata

    IPC分类号： G06F15/00

    CPC分类号： H04N1/6033

    摘要： An image forming apparatus includes; a chart data forming unit that forms density correcting chart data to be printed, in which reference density patterns and adjusting density patterns are arranged so that a connection angle, and the adjusting density patterns have different densities in the respective patterns; a printing unit that prints a density correcting chart in which the reference density patterns and the adjusting density patterns are arranged adjacent to each other in respective patterns; a receiving unit that receives an input of a density adjusting value of a desired pattern, on the basis of comparison of density between the reference density patterns and the adjusting density patterns which has been obtained from visual observation of a user on the printed density correcting chart; and a tone correcting unit that conducts tone correction of the desired pattern.

    摘要翻译： 图像形成装置包括： 图形数据形成单元，其形成要印刷的浓度校正图数据，其中布置参考密度图案和调节浓度图案，使得连接角度和调节浓度图案在各图案中具有不同的密度; 打印单元，其以相应的图案打印参考浓度图案和调整浓度图案彼此相邻布置的浓度校正图; 基于通过用户在目视观察印刷密度校正图上获得的参考密度图案和调节浓度图案之间的密度的比较来接收期望图案的浓度调节值的输入的接收单元 ; 以及进行所需图案的色调校正的色调校正单元。