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    SEMICONDUCTOR DEVICE AND METHOD OF OPERATING THE SEMICONDUCTOR DEVICE
    21.
    发明申请
    SEMICONDUCTOR DEVICE AND METHOD OF OPERATING THE SEMICONDUCTOR DEVICE 有权
    半导体器件和操作半导体器件的方法

    公开(公告)号：US20130069714A1

    公开(公告)日：2013-03-21

    申请号：US13550848

    申请日：2012-07-17

    申请人： Ho-jung Kim ,  U-in Chung ,  Jai-kwang Shin

    发明人： Ho-jung Kim ,  U-in Chung ,  Jai-kwang Shin

    IPC分类号： G05F1/10

    CPC分类号： H01L29/78684 ,  G11C29/12005

    摘要： A semiconductor device and a method of operating the semiconductor device. The semiconductor device includes a voltage generator configured to generate a test voltage, a graphene transistor configured to receive a gate-source voltage based on the test voltage, and a detector configured to detect whether the gate-source voltage is a Dirac voltage of the graphene transistor, and output a feedback signal applied to the voltage generator indicating whether the gate-source voltage is the Dirac voltage.

    摘要翻译： 一种半导体器件和操作半导体器件的方法。 半导体器件包括被配置为产生测试电压的电压发生器，被配置为基于测试电压接收栅极 - 源极电压的石墨烯晶体管，以及检测器，被配置为检测栅极 - 源极电压是否为石墨烯的狄拉克电压 并输出施加到电压发生器的反馈信号，指示栅极 - 源极电压是否为狄拉克电压。

    Semiconductor device
    22.
    发明申请
    Semiconductor device 有权
    半导体器件

    公开(公告)号：US20110221482A1

    公开(公告)日：2011-09-15

    申请号：US12923857

    申请日：2010-10-12

    申请人： Ho-jung Kim ,  Jong-seob Kim ,  Jai-Kwang Shin ,  Jae-joon Oh ,  Ki-ha Hong ,  In-jun Hwang ,  Hyuk-soon Choi

    发明人： Ho-jung Kim ,  Jong-seob Kim ,  Jai-Kwang Shin ,  Jae-joon Oh ,  Ki-ha Hong ,  In-jun Hwang ,  Hyuk-soon Choi

    IPC分类号： H03K3/01 ,  H03K17/00

    CPC分类号： H03K17/6871 ,  H02M1/08 ,  H02M3/158 ,  H02M3/337 ,  H02M2001/0074 ,  H03K2217/0081

    摘要： Provided is a semiconductor device that may include a switching device having a negative threshold voltage, and a driving unit between a power terminal and a ground terminal and providing a driving voltage for driving the switching device. The switching device may be connected to a virtual ground node having a virtual ground voltage that is greater than a ground voltage supplied from the ground terminal and may be turned on when a difference between the driving voltage and the virtual ground voltage is greater than the negative threshold voltage.

    摘要翻译： 提供一种半导体器件，其可以包括具有负阈值电压的开关器件，以及电源端子和接地端子之间的驱动单元，并且提供用于驱动开关器件的驱动电压。 开关器件可以连接到具有大于从接地端子提供的接地电压的虚拟接地电压的虚拟接地节点，并且当驱动电压和虚拟接地电压之间的差大于负值时，可以导通 阈值电压。

    Information storage devices including vertical nano wires
    25.
    发明授权
    Information storage devices including vertical nano wires 失效
    信息存储设备包括垂直纳米线

    公开(公告)号：US08089797B2

    公开(公告)日：2012-01-03

    申请号：US12659515

    申请日：2010-03-11

    申请人： Ho-jung Kim ,  Jai-kwang Shin ,  Sun-ae Seo ,  Sung-chul Lee

    发明人： Ho-jung Kim ,  Jai-kwang Shin ,  Sun-ae Seo ,  Sung-chul Lee

    IPC分类号： G11C19/00

    CPC分类号： G11C19/0808 ,  G11C11/161 ,  G11C11/1653 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1675

    摘要： A memory cell includes: a memory cell array unit having a plurality of nano wires arranged vertically on a substrate, each of the plurality of nano wires having a plurality of domains for storing information; a nano wire selection unit formed on the substrate and configured to select at least one of the plurality of nano wires; a domain movement control unit formed on the substrate and configured to control a domain movement operation with respect to at least one of the plurality of nano wires; and a read/write control unit formed on the substrate and configured to control at least one of a read operation and a write operation with respect to at least one of the plurality of nano wires.

    摘要翻译： 存储单元包括：存储单元阵列单元，具有垂直地布置在基板上的多个纳米线，所述多个纳米线中的每一个具有用于存储信息的多个域; 形成在所述基板上并被配置为选择所述多个纳米线中的至少一个的纳米线选择单元; 域移动控制单元，形成在所述基板上，并且被配置为控制相对于所述多个纳米线中的至少一个的域移动操作; 以及读/写控制单元，形成在所述基板上并被配置为控制关于所述多根纳米线中的至少一个的读取操作和写入操作中的至少一个。

    Nonvolatile logic circuit, integrated circuit including the nonvolatile logic circuit, and method of operating the integrated circuit
    26.
    发明申请
    Nonvolatile logic circuit, integrated circuit including the nonvolatile logic circuit, and method of operating the integrated circuit 有权
    非易失性逻辑电路，包括非易失性逻辑电路的集成电路和操作集成电路的方法

    公开(公告)号：US20110122709A1

    公开(公告)日：2011-05-26

    申请号：US12801502

    申请日：2010-06-11

    申请人： Ho-jung Kim ,  Jai-kwang Shin ,  Kwang-seok Kim ,  Kee-won Kim

    发明人： Ho-jung Kim ,  Jai-kwang Shin ,  Kwang-seok Kim ,  Kee-won Kim

    IPC分类号： G11C7/10 ,  H03K19/173

    CPC分类号： H03K19/1733 ,  G11C14/0054 ,  G11C14/0081 ,  G11C14/009 ,  H03K3/356008

    摘要： A nonvolatile logic circuit includes a latch unit including a pair of first and second latch nodes; and a pair of first and second nonvolatile memory cells electrically connected to the first and second of latch nodes, respectively. A write operation is performed on the first and second nonvolatile memory cells according to a direction of a current flowing through the first and second nonvolatile memory cells when a write enable signal is activated. The direction of flow of current determined based on data on the respective first and second latch nodes, and a logic value written on the first nonvolatile memory cells is different from a logic value written on the second nonvolatile memory cell.

    摘要翻译： 非易失性逻辑电路包括：锁存单元，包括一对第一和第二锁存节点; 以及分别电连接到第一和第二锁存节点的一对第一和第二非易失性存储单元。 当写入使能信号被激活时，根据流过第一和第二非易失性存储器单元的电流的方向在第一和第二非易失性存储器单元上执行写入操作。 基于相应的第一和第二锁存节点上的数据确定的电流的流动方向和写在第一非易失性存储器单元上的逻辑值与写入第二非易失性存储单元的逻辑值不同。

    Information storage devices including vertical nano wires
    27.
    发明申请
    Information storage devices including vertical nano wires 失效
    信息存储设备包括垂直纳米线

    公开(公告)号：US20110063885A1

    公开(公告)日：2011-03-17

    申请号：US12659515

    申请日：2010-03-11

    申请人： Ho-jung Kim ,  Jai-kwang Shin ,  Sun-ae Seo ,  Sung-chul Lee

    发明人： Ho-jung Kim ,  Jai-kwang Shin ,  Sun-ae Seo ,  Sung-chul Lee

    IPC分类号： G11C19/00 ,  G11C7/00

    CPC分类号： G11C19/0808 ,  G11C11/161 ,  G11C11/1653 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1675

    摘要： A memory cell includes: a memory cell array unit having a plurality of nano wires arranged vertically on a substrate, each of the plurality of nano wires having a plurality of domains for storing information; a nano wire selection unit formed on the substrate and configured to select at least one of the plurality of nano wires; a domain movement control unit formed on the substrate and configured to control a domain movement operation with respect to at least one of the plurality of nano wires; and a read/write control unit formed on the substrate and configured to control at least one of a read operation and a write operation with respect to at least one of the plurality of nano wires.

    摘要翻译： 存储单元包括：存储单元阵列单元，具有垂直地布置在基板上的多个纳米线，所述多个纳米线中的每一个具有用于存储信息的多个域; 形成在所述基板上并被配置为选择所述多个纳米线中的至少一个的纳米线选择单元; 域移动控制单元，形成在所述基板上，并且被配置为控制相对于所述多个纳米线中的至少一个的域移动操作; 以及读/写控制单元，形成在所述基板上并被配置为控制关于所述多根纳米线中的至少一个的读取操作和写入操作中的至少一个。

    Nonvolatile logic circuit, integrated circuit including the nonvolatile logic circuit, and method of operating the integrated circuit
    28.
    发明授权
    Nonvolatile logic circuit, integrated circuit including the nonvolatile logic circuit, and method of operating the integrated circuit 有权
    非易失性逻辑电路，包括非易失性逻辑电路的集成电路和操作集成电路的方法

    公开(公告)号：US08509004B2

    公开(公告)日：2013-08-13

    申请号：US12801502

    申请日：2010-06-11

    申请人： Ho-jung Kim ,  Jai-kwang Shin ,  Kwang-seok Kim ,  Kee-won Kim

    发明人： Ho-jung Kim ,  Jai-kwang Shin ,  Kwang-seok Kim ,  Kee-won Kim

    IPC分类号： G11C7/10

    CPC分类号： H03K19/1733 ,  G11C14/0054 ,  G11C14/0081 ,  G11C14/009 ,  H03K3/356008

    摘要： A nonvolatile logic circuit includes a latch unit including a pair of first and second latch nodes; and a pair of first and second nonvolatile memory cells electrically connected to the first and second of latch nodes, respectively. A write operation is performed on the first and second nonvolatile memory cells according to a direction of a current flowing through the first and second nonvolatile memory cells when a write enable signal is activated. The direction of flow of current determined based on data on the respective first and second latch nodes, and a logic value written on the first nonvolatile memory cells is different from a logic value written on the second nonvolatile memory cell.

    摘要翻译： 非易失性逻辑电路包括：锁存单元，包括一对第一和第二锁存节点; 以及分别电连接到第一和第二锁存节点的一对第一和第二非易失性存储单元。 当写入使能信号被激活时，根据流过第一和第二非易失性存储器单元的电流的方向在第一和第二非易失性存储器单元上执行写入操作。 基于相应的第一和第二锁存节点上的数据确定的电流的流动方向和写在第一非易失性存储器单元上的逻辑值与写入第二非易失性存储单元的逻辑值不同。

    Semiconductor device
    29.
    发明授权
    Semiconductor device 有权
    半导体器件

    公开(公告)号：US08508194B2

    公开(公告)日：2013-08-13

    申请号：US12923857

    申请日：2010-10-12

    申请人： Ho-jung Kim ,  Jong-seob Kim ,  Jai-kwang Shin ,  Jae-joon Oh ,  Ki-ha Hong ,  In-jun Hwang ,  Hyuk-soon Choi

    发明人： Ho-jung Kim ,  Jong-seob Kim ,  Jai-kwang Shin ,  Jae-joon Oh ,  Ki-ha Hong ,  In-jun Hwang ,  Hyuk-soon Choi

    IPC分类号： G05F1/10

    CPC分类号： H03K17/6871 ,  H02M1/08 ,  H02M3/158 ,  H02M3/337 ,  H02M2001/0074 ,  H03K2217/0081

    摘要： Provided is a semiconductor device that may include a switching device having a negative threshold voltage, and a driving unit between a power terminal and a ground terminal and providing a driving voltage for driving the switching device. The switching device may be connected to a virtual ground node having a virtual ground voltage that is greater than a ground voltage supplied from the ground terminal and may be turned on when a difference between the driving voltage and the virtual ground voltage is greater than the negative threshold voltage.

    摘要翻译： 提供一种半导体器件，其可以包括具有负阈值电压的开关器件，以及电源端子和接地端子之间的驱动单元，并且提供用于驱动开关器件的驱动电压。 开关器件可以连接到具有大于从接地端子提供的接地电压的虚拟接地电压的虚拟接地节点，并且当驱动电压和虚拟接地电压之间的差大于负值时，可以导通 阈值电压。