公开(公告)号：US20200328122A1

公开(公告)日：2020-10-15

申请号：US16843706

申请日：2020-04-08

Applicant: IMEC vzw

Inventor： Boon Teik Chan ,  Zheng Tao ,  Efrain Altamirano Sanchez

IPC: H01L21/8234 ,  H01L21/027 ,  H01L29/66

Abstract: A method for forming a mask layer above a semiconductor fin structure is disclosed. In one aspect the method includes forming a first set of spacers and a second set of spacers arranged at the side surfaces of the first set of spacers, providing a first filler material between the second set of spacers, etching a top portion of the first filler material to form recesses between the second set of spacers, and providing a second filler material in the recesses, the second filler material forming a set of sacrificial mask lines. Further, the method includes recessing a top portion of at least the first set of spacers, providing a mask layer material between the sacrificial mask lines, and removing the sacrificial mask lines and the first filler material.

公开(公告)号：US20200083090A1

公开(公告)日：2020-03-12

申请号：US16563747

申请日：2019-09-06

Applicant: IMEC VZW

Inventor： Boon Teik Chan ,  Efrain Altamirano Sanchez ,  Ryan Ryoung han Kim

IPC: H01L21/762 ,  H01L29/66 ,  H01L21/763 ,  H01L21/033 ,  H01L29/78

Abstract: A substrate includes on its surface an array of dual stack semiconductor fins, each fin comprising a monocrystalline first portion, a polycrystalline second portion, and a mask third portion. Trenches between the fins are filled with shallow trench isolation (STI) oxide and with polycrystalline material, after which the surface is planarized. Then a second mask is produced on the planarized surface, the second mask defining at least one opening, each defined opening extending across an exposed fin. A thermal oxidation is performed of the polycrystalline material on either side of the exposed fin in each defined opening, thereby producing two oxide strips in each defined opening. Using the second mask and the oxide strips as a mask for self-aligned etching, the material of the exposed dual stack fins is removed and subsequently replaced by an electrically isolating material, thereby creating gate cut structures.

公开(公告)号：US20190198643A1

公开(公告)日：2019-06-27

申请号：US16220361

申请日：2018-12-14

Applicant: IMEC vzw

Inventor： Boon Teik Chan ,  Anabela Veloso ,  Efrain Altamirano Sanchez ,  Zheng Tao

IPC: H01L29/66 ,  H01L29/08 ,  H01L29/78 ,  H01L21/3065

CPC classification number: H01L29/66666 ,  H01L21/3065 ,  H01L29/0847 ,  H01L29/42372 ,  H01L29/42392 ,  H01L29/6653 ,  H01L29/66742 ,  H01L29/7827 ,  H01L29/78642

Abstract: The disclosed technology generally relates to semiconductor devices and more particularly to a vertical channel device and a method of fabricating the same. According to one aspect, a method for fabricating a vertical channel device includes forming a vertical semiconductor structure including an upper portion, an intermediate portion and a lower portion, by etching a semiconductor layer stack arranged on a substrate. The semiconductor layer stack includes an upper semiconductor layer, an intermediate semiconductor layer and a lower semiconductor layer, wherein the intermediate semiconductor layer is formed of a material different from a material of the lower semiconductor layer and different from a material of the upper semiconductor layer. Forming the vertical semiconductor structure includes: etching the upper semiconductor layer to form the upper portion and the intermediate semiconductor layer to form the intermediate portion, detecting whether the etching has reached the lower semiconductor layer, and in response to detecting that the etching has reached the lower semiconductor layer, changing to a modified etching chemistry being different from an etching chemistry used during the etching of the intermediate semiconductor layer, and etching the lower semiconductor layer using the modified etching chemistry to form the lower portion. The modified etching chemistry is such that the lower portion is formed to present, along at least a part of the lower portion, a lateral dimension gradually increasing along a direction towards the substrate. The method further comprises forming a gate stack extending vertically along the intermediate portion to define a channel region of the vertical channel device.

公开(公告)号：US20190079384A1

公开(公告)日：2019-03-14

申请号：US16123058

申请日：2018-09-06

Applicant: IMEC VZW ,  Katholieke Universiteit Leuven, KU LEUVEN R&D

Inventor： Boon Teik Chan ,  Kim Vu Luong ,  Vicky Philipsen ,  Efrain Altamirano Sanchez ,  Kevin Vandersmissen

IPC: G03F1/24 ,  G03F1/80 ,  G03F1/58 ,  G03F7/20 ,  H01L21/768

Abstract: An example method for making a reticle includes providing an assembly. The assembly includes an extreme ultraviolet mirror and a cavity overlaying at least a bottom part of the extreme ultraviolet mirror. The method also includes at least partially filling the cavity with an extreme ultraviolet absorbing structure that includes a metallic material that includes an element selected from Ni, Co, Sb, Ag, In, and Sn, by forming the extreme ultraviolet absorbing structure selectively in the cavity.