公开(公告)号：US20250133744A1

公开(公告)日：2025-04-24

申请号：US18920207

申请日：2024-10-18

Applicant: IMEC VZW

Inventor： Jan Van Houdt

IPC: H10B53/20 ,  G11C11/22 ,  H10B53/30 ,  H10B53/40

Abstract: The present disclosure relates to a three-dimensional (3D) ferroelectric memory structure that includes a substrate, and a layer stack arranged on the substrate, the layer stack comprising multiple dielectric layers and first metallic layers alternatingly arranged along a first axis. A first ferroelectric layer extends through the layer stack and a second metallic layer extends through the layer stack adjacent to the first ferroelectric layer. The first ferroelectric layer forms, in combination with the plurality of first metallic layers and the second metallic layer, a plurality of first capacitive memory cells. The read-out may comprise applying a DC bias voltage to the first ferroelectric layer, which is lower than a voltage required to change a current polarization state of the first ferroelectric layer, detecting a capacitance of the first ferroelectric layer at the bias voltage and correlating it to a current polarization state of the first ferroelectric layer.

公开(公告)号：US20240206186A1

公开(公告)日：2024-06-20

申请号：US18540543

申请日：2023-12-14

Applicant: IMEC VZW

Inventor： Amey Mahadev Walke ,  Jan Van Houdt

IPC: H10B51/30 ,  H01L21/28 ,  H01L29/51 ,  H01L29/66 ,  H01L29/78 ,  H10B51/10

CPC classification number: H10B51/30 ,  H01L29/40111 ,  H01L29/516 ,  H01L29/6684 ,  H01L29/78391 ,  H10B51/10

Abstract: The disclosed technology relates to a ferroelectric field-effect transistor (FeFET) memory structure. The FeFET memory structure can include a substrate, including an insulator layer; a gate metal layer on the insulator layer; at least one ferroelectric material layer on the gate metal layer; and a layer structure comprising at least one wide bandgap semiconductor layer on the ferroelectric material layer, wherein the layer structure can include: a first section having a first height, and at least one second section having a second height that is smaller than the first height. The FeFET memory structure can further include a drain metal structure which is arranged on the first section of the layer structure, and one or more source metal structures, wherein each source metal structure is arranged on a respective second section of the layer structure.

公开(公告)号：US11968841B2

公开(公告)日：2024-04-23

申请号：US17650154

申请日：2022-02-07

Applicant: IMEC vzw

Inventor： Mihaela Ioana Popovici ,  Amey Mahadev Walke ,  Jan Van Houdt

IPC: H10B53/30 ,  H01L29/78 ,  H01L49/02

CPC classification number: H10B53/30 ,  H01L28/40 ,  H01L29/78391

Abstract: A ferroelectric device, for instance, a metal-ferroelectric-metal (MFM) capacitor, a ferroelectric random access memory (Fe-RAM), or a ferroelectric field effect transistor (FeFET), is provided. In one aspect, the ferroelectric device is based on hafnium zirconate (HZO). The ferroelectric device can include a first electrode and a second electrode, and a doped HZO layer, which is arranged between the first electrode and the second electrode. The doped HZO layer can include a ferroelectric layer and at least two non-zero remnant polarization charge states. The doped HZO layer can be doped with at least two different elements selected from the lanthanide series, or with a combination of at least one element selected from the lanthanide series and at least one rare earth element.

公开(公告)号：US20230197807A1

公开(公告)日：2023-06-22

申请号：US18069010

申请日：2022-12-20

Applicant: IMEC VZW

Inventor： Jan Van Houdt

IPC: H01L29/423 ,  H10B51/30 ,  H01L29/78 ,  H01L21/28 ,  H01L29/66

CPC classification number: H01L29/4232 ,  H01L27/1159 ,  H01L29/6684 ,  H01L29/40111 ,  H01L29/78391

Abstract: The present disclosure provides a ferroelectric field-effect transistor comprising: a substrate comprising a source region, a channel, and a drain region; a ferroelectric material arranged on a first portion of the channel and a portion of the drain region; a program gate arranged on the ferroelectric material and being at least coextensive with the first portion of the channel; a gate dielectric arranged on a portion of the source region and a second portion of the channel; and a select gate arranged on the gate dielectric and being at least coextensive with said portion of the source region and the second portion of the channel; wherein a well of the substrate extending under the whole channel has a uniform doping level.

公开(公告)号：US10211312B2

公开(公告)日：2019-02-19

申请号：US15230289

申请日：2016-08-05

Applicant: IMEC VZW

Inventor： Jan Van Houdt ,  Voon Yew Thean

IPC: H01L29/51 ,  H01L29/78 ,  H01L29/66 ,  H01L21/28 ,  H01L21/02

Abstract: The disclosed technology generally relates to semiconductor devices, and more particularly to a non-volatile ferroelectric memory device and to methods of fabricating the same. In one aspect, a non-volatile memory device includes a high dielectric constant layer (high-k) layer or a metal layer on a semiconductor substrate. The non-volatile memory device additionally includes a two-dimensional (2D) semiconductor channel layer interposed between the high-k layer or metal layer and a ferroelectric layer. The non-volatile memory device additionally includes a metal gate layer on the ferroelectric layer, and further includes a source region and a drain region each electrically coupled to the 2D semiconductor channel layer.

公开(公告)号：US10211223B2

公开(公告)日：2019-02-19

申请号：US14998227

申请日：2015-12-23

Applicant: IMEC VZW

Inventor： Jan Van Houdt ,  Pieter Blomme

IPC: G11C11/22 ,  H01L21/28 ,  H01L29/51 ,  H01L29/66 ,  H01L29/78 ,  H01L27/1159 ,  H01L27/11597

Abstract: The disclosed technology generally relates to semiconductor devices, and more particularly to a ferroelectric memory device and a method of manufacturing and using the same. In one aspect, a vertical ferroelectric memory device includes a stack of horizontal layers formed on a semiconductor substrate, where the stack of layers includes a plurality gate electrode layers alternating with a plurality of insulating layers. A vertical structure extends vertically through the stack of horizontal layers, where the vertical structure has a vertical channel structure and a sidewall having formed thereon a vertical transition metal oxide (TMO) ferroelectric layer. A memory cell is formed at each of overlapping regions between the gate electrode layers and the vertical channel structure.

公开(公告)号：US09847109B2

公开(公告)日：2017-12-19

申请号：US15369204

申请日：2016-12-05

Applicant: IMEC VZW

Inventor： Jan Van Houdt

IPC: G11C16/04 ,  G11C7/06 ,  H01L29/51 ,  H01L29/78 ,  H01L29/788 ,  H01L29/792

CPC classification number: G11C7/06 ,  G11C16/0441 ,  G11C16/045 ,  G11C16/28 ,  H01L28/00 ,  H01L29/516 ,  H01L29/78 ,  H01L29/78391 ,  H01L29/788 ,  H01L29/792

Abstract: The present disclosure relates to a memory cell, a memory array, and methods for writing a memory cell. In an example embodiment, a memory cell comprises a first transistor, a second transistor, and a differential sense amplifier. The first transistor is a Vt-modifiable n-channel transistor and the second transistor is a Vt-modifiable p-channel transistor, each transistor having first and second main electrodes. The first main electrodes of the first and second transistors are connected together. The differential sense amplifier is connected to the second main electrodes of the first and the second transistor. The differential sense amplifier is adapted for sensing the current difference between the first transistor and the second transistor.

公开(公告)号：US20170040331A1

公开(公告)日：2017-02-09

申请号：US15230289

申请日：2016-08-05

Applicant: IMEC VZW

Inventor： Jan Van Houdt ,  Voon Yew Thean

IPC: H01L27/115 ,  H01L29/66 ,  H01L29/51 ,  H01L29/78

CPC classification number: H01L29/516 ,  H01L21/0242 ,  H01L21/02425 ,  H01L21/02568 ,  H01L21/28291 ,  H01L29/6684 ,  H01L29/78391

Abstract: The disclosed technology generally relates to semiconductor devices, and more particularly to a non-volatile ferroelectric memory device and to methods of fabricating the same. In one aspect, a non-volatile memory device includes a high dielectric constant layer (high-k) layer or a metal layer on a semiconductor substrate. The non-volatile memory device additionally includes a two-dimensional (2D) semiconductor channel layer interposed between the high-k layer or metal layer and a ferroelectric layer. The non-volatile memory device additionally includes a metal gate layer on the ferroelectric layer, and further includes a source region and a drain region each electrically coupled to the 2D semiconductor channel layer.

Abstract translation: 所公开的技术通常涉及半导体器件，更具体地涉及非挥发性铁电存储器件及其制造方法。 一方面，非易失性存储器件包括半导体衬底上的高介电常数层（高k）层或金属层。 非易失性存储器件还包括插入在高k层或金属层与铁电层之间的二维（2D）半导体沟道层。 非易失性存储器件还包括在铁电层上的金属栅极层，并且还包括电源耦合到2D半导体沟道层的源极区域和漏极区域。

公开(公告)号：US20220254795A1

公开(公告)日：2022-08-11

申请号：US17650154

申请日：2022-02-07

Applicant: IMEC vzw

Inventor： Mihaela Ioana Popovici ,  Amey Mahadev Walke ,  Jan Van Houdt

IPC: H01L27/11507 ,  H01L49/02 ,  H01L29/78

Abstract: A ferroelectric device, for instance, a metal-ferroelectric-metal (MFM) capacitor, a ferroelectric random access memory (Fe-RAM), or a ferroelectric field effect transistor (FeFET), is provided. In one aspect, the ferroelectric device is based on hafnium zirconate (HZO). The ferroelectric device can include a first electrode and a second electrode, and a doped HZO layer, which is arranged between the first electrode and the second electrode. The doped HZO layer can include a ferroelectric layer and at least two non-zero remnant polarization charge states. The doped HZO layer can be doped with at least two different elements selected from the lanthanide series, or with a combination of at least one element selected from the lanthanide series and at least one rare earth element.

公开(公告)号：US20200083234A1

公开(公告)日：2020-03-12

申请号：US16565112

申请日：2019-09-09

Applicant: IMEC vzw

Inventor： Shairfe Muhammad Salahuddin ,  Jan Van Houdt ,  Julien Ryckaert ,  Alessio Spessot

IPC: H01L27/1159 ,  H01L27/108 ,  G11C11/4096 ,  G11C11/22 ,  H01L27/11587 ,  H01L27/11592

Abstract: The disclosed technology is generally directed to semiconductor integrated circuit devices and more particularly to a three-transistor random access memory (3T RAM) device, and a method of fabricating and operating the same. In one aspect, a 3T RAM cell includes a ferroelectric-based field effect transistor (FeFET) having a first gate connected as a storage node and a second transistor connected between the FeFET and a read bit line having a second gate connected to a read word line. The 3T RAM cell also includes a third transistor connected between the storage node and a write bit line having a third gate connected to a write word line.