公开(公告)号：US10211223B2

公开(公告)日：2019-02-19

申请号：US14998227

申请日：2015-12-23

Applicant: IMEC VZW

Inventor： Jan Van Houdt ,  Pieter Blomme

IPC: G11C11/22 ,  H01L21/28 ,  H01L29/51 ,  H01L29/66 ,  H01L29/78 ,  H01L27/1159 ,  H01L27/11597

Abstract: The disclosed technology generally relates to semiconductor devices, and more particularly to a ferroelectric memory device and a method of manufacturing and using the same. In one aspect, a vertical ferroelectric memory device includes a stack of horizontal layers formed on a semiconductor substrate, where the stack of layers includes a plurality gate electrode layers alternating with a plurality of insulating layers. A vertical structure extends vertically through the stack of horizontal layers, where the vertical structure has a vertical channel structure and a sidewall having formed thereon a vertical transition metal oxide (TMO) ferroelectric layer. A memory cell is formed at each of overlapping regions between the gate electrode layers and the vertical channel structure.

公开(公告)号：US20160043096A1

公开(公告)日：2016-02-11

申请号：US14820459

申请日：2015-08-06

Applicant: IMEC VZW

Inventor： Pieter Blomme

IPC: H01L27/115 ,  H01L29/423 ,  H01L21/02 ,  H01L21/28

CPC classification number: H01L27/11556 ,  H01L21/02592 ,  H01L21/02667 ,  H01L29/40114 ,  H01L29/42324 ,  H01L29/42364 ,  H01L29/66825 ,  H01L29/7889

Abstract: The disclosed technology generally relates to fabricating semiconductor devices and more particularly to fabricating a floating-gate based memory device. In one aspect, a method of fabricating a memory device comprises forming a stack of horizontal layers comprising alternating sacrificial layers of a first type and sacrificial layers of a second type; forming a vertical opening through the horizontal stack of layers; forming a first vertical dielectric layer on a sidewall of the vertical opening; forming a vertical floating gate layer on the first vertical dielectric layer; forming a second vertical dielectric layer on the vertical floating gate layer; filling the vertical opening with a channel material; forming cavities of a first type by removing the sacrificial layers of the second type to expose the first vertical dielectric layer; removing portions of the first vertical dielectric layer and the vertical floating gate layer at locations adjacent to the cavities of the first type, such that portions of the second vertical dielectric layer are exposed; filling the cavities of the first type with an isolating material; forming cavities of a second type by removing the sacrificial layers of the first type, wherein the cavities of the second type exposes portions of the first vertical dielectric layer; forming a third dielectric layer in the cavities of the second type, wherein the third dielectric layer is formed on the first vertical dielectric layer; and forming a conductive material in the cavities of the second type.

Abstract translation: 所公开的技术通常涉及制造半导体器件，更具体地涉及制造基于浮栅的存储器件。 在一个方面，一种制造存储器件的方法包括形成水平层的堆叠，其包括第一类型的交替牺牲层和第二类型的牺牲层; 通过层的水平叠层形成垂直开口; 在所述垂直开口的侧壁上形成第一垂直介电层; 在所述第一垂直介电层上形成垂直浮栅层; 在所述垂直浮栅层上形成第二垂直介电层; 用通道材料填充垂直开口; 通过去除所述第二类型的牺牲层以暴露所述第一垂直介电层来形成第一类型的空腔; 在与第一类型的空腔相邻的位置处去除第一垂直介电层和垂直浮动栅极的部分，使得第二垂直介电层的部分暴露; 用隔离材料填充第一类型的空腔; 通过去除第一类型的牺牲层来形成第二类型的空腔，其中第二类型的空腔暴露第一垂直介电层的部分; 在所述第二类型的空腔中形成第三电介质层，其中所述第三电介质层形成在所述第一垂直介电层上; 以及在所述第二类型的空腔中形成导电材料。

公开(公告)号：US20200006380A1

公开(公告)日：2020-01-02

申请号：US16563114

申请日：2019-09-06

Applicant: IMEC vzw

Inventor： Jan Van Houdt ,  Pieter Blomme

IPC: H01L27/11582 ,  H01L21/28 ,  H01L21/02 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/768 ,  H01L27/11521 ,  H01L27/11556 ,  H01L27/11568 ,  H01L27/24 ,  H01L29/10 ,  H01L29/66 ,  H01L45/00

Abstract: The disclosed technology relates generally to semiconductor devices and more particularly to three dimensional semiconductor memory devices, such as vertical three dimensional non-volatile memory devices. In one aspect, a vertical three-dimensional semiconductor memory device comprises a memory block comprising at least one memory hole formed through a stack of alternating layers of control gate layers and dielectric layers, wherein the memory hole is filled with a plurality of materials forming at least one memory cell. The semiconductor memory device additionally includes at least one trench formed through the stack so as to define part of a boundary of the memory block, wherein a sidewall of the trench comprises the control gate layers each having at least a portion that is in part laterally recessed relative to vertically adjacent dielectric layers, and wherein the trench is filled with an electrically conductive material.

公开(公告)号：US10418377B2

公开(公告)日：2019-09-17

申请号：US15855692

申请日：2017-12-27

Applicant: IMEC VZW

Inventor： Jan Van Houdt ,  Pieter Blomme

IPC: H01L27/11582 ,  H01L21/28 ,  H01L21/02 ,  H01L27/11521 ,  H01L21/768 ,  H01L29/10 ,  H01L21/3213 ,  H01L29/66 ,  H01L27/11556 ,  H01L27/11568 ,  H01L21/311 ,  H01L45/00 ,  H01L27/24 ,  H01L27/1159 ,  H01L27/11597

Abstract: The disclosed technology relates generally to semiconductor devices and more particularly to three dimensional semiconductor memory devices, such as vertical three dimensional non-volatile memory devices. In one aspect, a method of fabricating a memory device comprises providing, on a substrate, an alternating stack of control gate layers and dielectric layers. The method additionally includes forming a memory block. comprising forming at least one memory hole through the alternating stack, where the at least one memory hole comprises on its sidewalls a stack of a programmable material, a channel material and a dielectric material, thereby forming at least one memory cell. The method additionally comprises removing a portion of the alternating stack to form at least one trench, where the at least one trench forms at least part of a boundary of the memory block. The method additionally comprises partially removing the control gate layers exposed at a sidewall of the at least one trench, thereby forming recesses in the control gate layers. The method further comprises filling the recesses with an electrically conductive material, thereby forming electrically conductive plugs. In another aspect, a device formed using the method is also provided.

公开(公告)号：US20180233512A1

公开(公告)日：2018-08-16

申请号：US15855692

申请日：2017-12-27

Applicant: IMEC VZW

Inventor： Jan Van Houdt ,  Pieter Blomme

IPC: H01L27/11582 ,  H01L21/311 ,  H01L21/28 ,  H01L21/02 ,  H01L27/11521 ,  H01L21/768 ,  H01L29/10 ,  H01L21/3213 ,  H01L29/66 ,  H01L27/11556 ,  H01L27/11568

CPC classification number: H01L27/11582 ,  H01L21/02636 ,  H01L21/31111 ,  H01L21/32133 ,  H01L21/76802 ,  H01L21/76877 ,  H01L21/76897 ,  H01L27/11521 ,  H01L27/11556 ,  H01L27/11568 ,  H01L27/1159 ,  H01L27/11597 ,  H01L27/2463 ,  H01L27/2481 ,  H01L27/249 ,  H01L29/1037 ,  H01L29/40114 ,  H01L29/40117 ,  H01L29/66545 ,  H01L45/04 ,  H01L45/06 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/124

Abstract: The disclosed technology relates generally to semiconductor devices and more particularly to three dimensional semiconductor memory devices, such as vertical three dimensional non-volatile memory devices. In one aspect, a method of fabricating a memory device comprises providing, on a substrate, an alternating stack of control gate layers and dielectric layers. The method additionally includes forming a memory block. comprising forming at least one memory hole through the alternating stack, where the at least one memory hole comprises on its sidewalls a stack of a programmable material, a channel material and a dielectric material, thereby forming at least one memory cell. The method additionally comprises removing a portion of the alternating stack to form at least one trench, where the at least one trench forms at least part of a boundary of the memory block. The method additionally comprises partially removing the control gate layers exposed at a sidewall of the at least one trench, thereby forming recesses in the control gate layers. The method further comprises filling the recesses with an electrically conductive material, thereby forming electrically conductive plugs. In another aspect, a device formed using the method is also provided.

公开(公告)号：US20160181259A1

公开(公告)日：2016-06-23

申请号：US14998227

申请日：2015-12-23

Applicant: IMEC VZW

Inventor： Jan Van Houdt ,  Pieter Blomme

IPC: H01L27/115 ,  G11C11/22 ,  H01L21/28

CPC classification number: H01L27/1159 ,  G11C11/2273 ,  H01L21/28291 ,  H01L27/11597 ,  H01L29/516 ,  H01L29/6684 ,  H01L29/78391

Abstract: The disclosed technology generally relates to semiconductor devices, and more particularly to a ferroelectric memory device and a method of manufacturing and using the same. In one aspect, a vertical ferroelectric memory device includes a stack of horizontal layers formed on a semiconductor substrate, where the stack of layers includes a plurality gate electrode layers alternating with a plurality of insulating layers. A vertical structure extends vertically through the stack of horizontal layers, where the vertical structure has a vertical channel structure and a sidewall having formed thereon a vertical transition metal oxide (TMO) ferroelectric layer. A memory cell is formed at each of overlapping regions between the gate electrode layers and the vertical channel structure.

Abstract translation: 所公开的技术通常涉及半导体器件，更具体地涉及铁电存储器件及其制造和使用方法。 一方面，垂直铁电存储器件包括形成在半导体衬底上的一叠水平层，其中堆叠层包括与多个绝缘层交替的多个栅极电极层。 垂直结构垂直延伸穿过水平层堆叠，其中垂直结构具有垂直沟道结构，并且在其上形成有垂直过渡金属氧化物（TMO）铁电层的侧壁。 在栅极电极层和垂直沟道结构之间的每个重叠区域处形成存储单元。