公开(公告)号：US11244949B2

公开(公告)日：2022-02-08

申请号：US16441725

申请日：2019-06-14

Applicant: IMEC vzw

Inventor： Pieter Weckx ,  Juergen Boemmels ,  Julien Ryckaert

IPC: H01L29/76 ,  H01L27/11 ,  G11C5/02 ,  G11C5/06 ,  G11C11/412 ,  H01L21/822 ,  H01L21/8238

Abstract: The disclosed technology generally relates to semiconductor devices and more particularly to a semiconductor device comprising stacked complementary transistor pairs. In one aspect, a semiconductor device comprises first and second sets of transistors comprising a pass transistor and a stacked complementary transistor pair of a lower transistor and an upper transistor, wherein first transistor comprises a semiconductor channel extending along a horizontal first fin track, and each second transistor comprises a semiconductor channel extending along a second fin track parallel to the first fin track, and wherein the semiconductor channels of the pass transistors and of the lower transistors are arranged at a first level and the semiconductor channels of said upper transistors are arranged at a second level, a first tall gate electrode forming a common gate for the first complementary transistor pair and arranged along a horizontal first gate track, and a first short gate electrode forming a gate for the first pass transistor and arranged along a second gate track, a second tall gate electrode forming a common gate for the second complementary transistor pair and arranged along the second gate track, a second short gate electrode forming a gate for the second pass transistor and arranged along the first gate track, first and second contact arrangements forming a common drain contact for the transistors of the first set and the second set, respectively, and first and second cross-couple contacts extending horizontally between and interconnecting the first tall gate electrode and the second contact arrangement, and the second tall gate electrode and the first contact arrangement, respectively.

公开(公告)号：US11211404B2

公开(公告)日：2021-12-28

申请号：US16565112

申请日：2019-09-09

Applicant: IMEC vzw

Inventor： Shairfe Muhammad Salahuddin ,  Jan Van Houdt ,  Julien Ryckaert ,  Alessio Spessot

IPC: G11C11/22 ,  H01L27/1159 ,  G11C11/4096 ,  H01L27/108 ,  H01L27/11587 ,  H01L27/11592

Abstract: The disclosed technology is generally directed to semiconductor integrated circuit devices and more particularly to a three-transistor random access memory (3T RAM) device, and a method of fabricating and operating the same. In one aspect, a 3T RAM cell includes a ferroelectric-based field effect transistor (FeFET) having a first gate connected as a storage node and a second transistor connected between the FeFET and a read bit line having a second gate connected to a read word line. The 3T RAM cell also includes a third transistor connected between the storage node and a write bit line having a third gate connected to a write word line.

公开(公告)号：US20200312726A1

公开(公告)日：2020-10-01

申请号：US16836653

申请日：2020-03-31

Applicant: IMEC vzw

Inventor： Anabela Veloso ,  Trong Huynh Bao ,  Julien Ryckaert ,  Raf Appeltans

IPC: H01L21/8234 ,  H01L27/088

Abstract: A method of fabricating a semiconductor device is disclosed. In one aspect, the method includes forming, in a vertical channel field-effect transistor (FET) device region, a vertical channel FET device including a first semiconductor structure including a lower source/drain portion, an upper source/drain portion, a first channel portion extending vertically and intermediate the source/drain portions and a gate structure extending along the channel portion and, in a horizontal channel FET device region, a horizontal channel FET device comprising a second semiconductor structure including a first source/drain portion, a second source/drain portion, a second channel portion extending horizontally and intermediate the source/drain portions, and a gate structure extending across the channel portion.

公开(公告)号：US10748815B2

公开(公告)日：2020-08-18

申请号：US16663796

申请日：2019-10-25

Applicant: IMEC vzw

Inventor： Juergen Boemmels ,  Julien Ryckaert

IPC: H01L21/8234 ,  H01L29/423

Abstract: The present disclosure relates to three dimensional (3D) transistor structures and methods of forming the same. In an aspect, a method comprises providing a vertical stack of alternating layers of channel material and dummy material, forming a first set of fins on the stack, and forming a second fin above the first set of fins, the second fin extending orthogonal to the first set of fins. Further, the first set of fins is cut into a set of fin portions, using the second fin and a first sidewall spacers as an etch mask, and second sidewall spacers are formed on the second fin. These structures are used to form a 3D structure of channel regions and source/drain regions forming transistor structures. Advantageously, the 3D semiconductor structure is manufactured using a relatively low number of mask layers per transistor which decreases manufacturing costs.

公开(公告)号：US10720363B2

公开(公告)日：2020-07-21

申请号：US15977381

申请日：2018-05-11

Applicant: IMEC VZW ,  Vrije Universiteit Brussel

Inventor： Julien Ryckaert ,  Naoto Horiguchi ,  Dan Mocuta ,  Trong Huynh Bao

IPC: H01L21/8234 ,  H01L21/8238 ,  H01L21/285 ,  H01L21/306 ,  H01L29/78 ,  H01L21/762 ,  H01L23/528 ,  H01L27/11 ,  H01L27/092 ,  H01L29/06 ,  H01L29/45 ,  H01L21/308 ,  H01L29/66 ,  H01L29/786

Abstract: The disclosed technology generally relates to semiconductor fabrication and more particularly to forming vertical transistor devices. In an aspect, a method of forming a vertical transistor device includes forming, on a substrate, a fin comprising a stack including a first layer, a second layer formed above the first layer and a third layer formed above the second layer. The method additionally includes forming a gate layer serving as an etch mask above the third layer. The method further includes etching the second and third layers of the fin using the gate layer as the etch mask to form a pillar. First and third layers of the pillar define a source region and a drain region, respectively, of the vertical transistor device. A second layer of the pillar defines a channel region of the vertical transistor device. The gate layer comprises a gate electrode arranged on at least one sidewall of the second layer.

公开(公告)号：US10607896B2

公开(公告)日：2020-03-31

申请号：US15591944

申请日：2017-05-10

Applicant: IMEC VZW

Inventor： Lars-Ake Ragnarsson ,  Hendrik F.W. Dekkers ,  Tom Schram ,  Julien Ryckaert ,  Naoto Horiguchi ,  Mustafa Badaroglu

IPC: H01L21/8238 ,  H01L21/768 ,  H01L29/66 ,  H01L21/84 ,  H01L21/02

Abstract: The disclosed technology generally relates to semiconductor devices and more particularly to a gate structure for a semiconductor device, and to methods of forming the same. In an aspect a method for forming a gate structure includes forming a first set of one or more semiconductor features and a second set of one or more semiconductor features. The method additionally includes forming a sacrificial gate extending across the semiconductor features of the first set and the semiconductor features of the second set. The method additionally includes forming a hole by etching the sacrificial gate, wherein the sacrificial gate is divided into a first sacrificial gate section and a second sacrificial gate section, forming a barrier in the hole by depositing a barrier material in the hole, removing the first sacrificial gate section and the second sacrificial gate section by etching wherein a first trench section is formed and a second trench section is formed, forming a first gate conductor in the first trench section and the second trench section, forming a mask above the second trench section, the mask exposing the first trench section, etching the first gate conductor in the first trench section, wherein the mask and the barrier counteracts etching of the first gate conductor in the second trench section, and forming a second gate conductor in the first trench section.

公开(公告)号：US10522552B2

公开(公告)日：2019-12-31

申请号：US15980604

申请日：2018-05-15

Applicant: IMEC VZW

Inventor： Julien Ryckaert ,  Naoto Horiguchi ,  Dan Mocuta ,  Trong Huynh Bao

IPC: H01L21/8234 ,  H01L27/11 ,  H01L27/088 ,  H01L29/66 ,  H01L29/417 ,  H01L29/78 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/786

Abstract: The disclosed technology generally relates semiconductor devices and more particularly to a vertical transistor device, and a method of fabricating the same. In one aspect, the method includes providing, on a substrate, a fin formed of a stack of a first layer, a second layer and a third layer, wherein the second layer is positioned above the first layer and the third layer is positioned above the second layer. The method additionally includes forming a dielectric on the sidewalls of the first and third layers of the fin selectively against a sidewall of the second layer, and the method additionally includes forming a gate contacting layer for contacting a sidewall of the second layer. The first and third layers define a source region and a drain region, respectively, of the vertical transistor device. The second layer defines a channel region of the vertical transistor device. The dielectric on the sidewalls of the first and third layers electrically isolates the source and drain regions from the gate contacting layer.

公开(公告)号：US10332588B2

公开(公告)日：2019-06-25

申请号：US15851531

申请日：2017-12-21

Applicant: IMEC VZW ,  Vrije Universiteit Brussel

Inventor： Trong Huynh Bao ,  Julien Ryckaert ,  Praveen Raghavan ,  Pieter Weckx

IPC: G11C11/412 ,  H01L27/11 ,  H01L29/423 ,  G11C11/408 ,  H01L29/08 ,  H01L27/06 ,  H01L29/06

Abstract: In an aspect of the disclosed technology, a SRAM device includes a first stack of transistors and a second stack of transistors arranged on a substrate. Each of the first and second stacks includes a pull-up transistor, a pull-down transistor and a pass transistor, where each of the transistors includes a horizontally extending channel. In each of the first and second stacks, the pull-up transistor and the pull-down transistor have a common gate electrode extending vertically therebetween, and the pass transistor has a gate electrode separated from the common gate electrode. A source/drain of each of the pull-up transistor and the pull-down transistor and a source/drain of the pass transistor included in one of the first stack and the second stack are electrically interconnected with the common gate electrode of the pull-up transistor and the pull-down transistor included in the other of the first stack and the second stack.

公开(公告)号：US20180102365A1

公开(公告)日：2018-04-12

申请号：US15729532

申请日：2017-10-10

Applicant: IMEC vzw

Inventor： Jan Van Houdt ,  Julien Ryckaert ,  Hyungrock Oh

IPC: H01L27/108 ,  H01L21/8254 ,  G11C11/405

CPC classification number: H01L27/108 ,  G11C5/025 ,  G11C5/04 ,  G11C5/06 ,  G11C11/405 ,  G11C11/4076 ,  G11C11/4094 ,  G11C11/4097 ,  G11C13/004 ,  G11C13/0069 ,  G11C2213/71 ,  H01L21/8254 ,  H01L23/528 ,  H01L25/0657 ,  H01L27/10805 ,  H01L28/60

Abstract: The disclosed technology relates to a memory device for a dynamic random access memory, or DRAM. In one aspect, the memory device includes a substrate supporting a semiconductor device layer in which a plurality of semiconductor devices are formed. The memory device may further include an interconnection portion formed above the substrate and including a number of metallization levels and dielectric layers, the interconnection portion being adapted to interconnect said semiconductor devices. The memory device may further include a plurality of bit cell stacks arranged in the interconnection portion, each bit cell stack including a plurality of bit cells. Further, such bit cells may include elements such as a charge storage element, a write transistor, and a read transistor.

公开(公告)号：US20170330801A1

公开(公告)日：2017-11-16

申请号：US15591944

申请日：2017-05-10

Applicant: IMEC VZW

Inventor： Lars-Ake Ragnarsson ,  Hendrik F.W. Dekkers ,  Tom Schram ,  Julien Ryckaert ,  Naoto Horiguchi ,  Mustafa Badaroglu

IPC: H01L21/8238 ,  H01L21/02

CPC classification number: H01L21/823857 ,  H01L21/0214 ,  H01L21/022 ,  H01L21/76895 ,  H01L21/823821 ,  H01L21/823842 ,  H01L21/823871 ,  H01L21/823878 ,  H01L21/845 ,  H01L29/66545

Abstract: The disclosed technology generally relates to semiconductor devices and more particularly to a gate structure for a semiconductor device, and to methods of forming the same. In an aspect a method for forming a gate structure includes forming a first set of one or more semiconductor features and a second set of one or more semiconductor features. The method additionally includes forming a sacrificial gate extending across the semiconductor features of the first set and the semiconductor features of the second set. The method additionally includes forming a hole by etching the sacrificial gate, wherein the sacrificial gate is divided into a first sacrificial gate section and a second sacrificial gate section, forming a barrier in the hole by depositing a barrier material in the hole, removing the first sacrificial gate section and the second sacrificial gate section by etching wherein a first trench section is formed and a second trench section is formed, forming a first gate conductor in the first trench section and the second trench section, forming a mask above the second trench section, the mask exposing the first trench section, etching the first gate conductor in the first trench section, wherein the mask and the barrier counteracts etching of the first gate conductor in the second trench section, and forming a second gate conductor in the first trench section.