公开(公告)号：US10325665B2

公开(公告)日：2019-06-18

申请号：US15836124

申请日：2017-12-08

Applicant: INTEL CORPORATION

Inventor： Richard Fastow ,  Xin Sun ,  Uday Chandrasekhar ,  Krishna K. Parat ,  Camila Jaramillo ,  Purval S. Sule ,  Aliasgar S. Madraswala

IPC: G11C5/14 ,  G11C16/28 ,  G11C16/16 ,  G11C16/34 ,  G11C11/4074 ,  G11C16/04

Abstract: A controller for a NAND memory array is presented. In embodiments, the controller may include circuitry to provide bias voltages to a NAND memory array that includes two or more decks of memory cells, and an output interface coupled to the circuitry and to wordlines (WLs) of the memory array. In embodiments, the circuitry, in a deck erase operation may: apply a first set of bias voltages via the output interface to active WLs of at least a first deck of the two or more decks of memory cells to be erased; and apply a second set of bias voltages via the output interface to active WLs of at least a second deck of the two or more decks of memory cells not to be erased, wherein the first set of bias voltages is lower than the second set of bias voltages.

公开(公告)号：US10242734B1

公开(公告)日：2019-03-26

申请号：US15720492

申请日：2017-09-29

Applicant: INTEL CORPORATION

Inventor： Ali Khakifirooz ,  Rohit S. Shenoy ,  Pranav Kalavade ,  Aliasgar S. Madraswala ,  Yogesh B. Wakchaure

IPC: G11C16/04 ,  G11C11/56 ,  G11C16/34 ,  G11C7/10

Abstract: Provided are techniques for resuming storage die programming after power loss. In response to receipt of an indication of the power loss, data that was to be programmed to multi-level cell NAND blocks are copied to single level cell NAND blocks and a pulse number at which programming was interrupted is stored. In response to receipt of an indication to resume from the power loss, the data is copied from the single level cell NAND blocks to a page buffer, the pulse number is retrieved, and programming of the multi-level cell NAND blocks is resumed at the retrieved pulse number using the data in the page buffer.

公开(公告)号：US10203884B2

公开(公告)日：2019-02-12

申请号：US15085291

申请日：2016-03-30

Applicant: Intel Corporation

Inventor： Aliasgar S. Madraswala ,  Yogesh B. Wakchaure ,  Camila Jaramillo ,  Trupti Bemalkhedkar

IPC: G06F3/06 ,  G11C16/22

Abstract: A disclosed example to use an erase-suspend feature with a memory device includes sending, by a memory host controller, an erase-suspend enable setting and an erase segment duration value to the memory device. The erase-suspend enable setting is to cause the memory device to perform an erase operation as a plurality of erase segments and to suspend the erase operation between the erase segments. The erase segment duration value is to specify a length of time for the erase segments. The memory host controller initiates an erase operation to be performed at the memory device. When the erase operation is suspended, the memory host controller initiates a second memory operation to be performed at the memory device. After the memory host controller determines that the second memory operation is complete, the memory host controller initiates resumption of the erase operation.

公开(公告)号：US20190043596A1

公开(公告)日：2019-02-07

申请号：US15838202

申请日：2017-12-11

Applicant: Intel Corporation

Inventor： Aliasgar S. Madraswala ,  Xin Guo ,  Ali Khakifirooz ,  Pranav Kalavade ,  Sagar Upadhyay

IPC: G11C16/34 ,  G11C16/04 ,  G11C11/56 ,  G11C16/10 ,  G11C16/22

Abstract: Embodiments of the present disclosure may relate to a memory controller that may include a memory interface and a logic circuitry component coupled with the memory interface. In some embodiments, the logic circuitry component is to program one or more NAND cells of a multi-level NAND memory array via the memory interface with a first set of data in a first pass, determine a first temperature of the multi-level NAND memory array in association with the first pass, determine a second temperature of the multi-level NAND memory array, determine a temperature difference between the second temperature and the first temperature, and perform one or more operations based at least in part on a result of the determination of the temperature difference. Other embodiments may be described and/or claimed.

公开(公告)号：US20170285969A1

公开(公告)日：2017-10-05

申请号：US15085291

申请日：2016-03-30

Applicant: Intel Corporation

Inventor： Aliasgar S. Madraswala ,  Yogesh B. Wakchaure ,  Camila Jaramillo ,  Trupti Bemalkhedkar

IPC: G06F3/06 ,  G11C16/22

CPC classification number: G06F3/0613 ,  G06F3/0634 ,  G06F3/0652 ,  G06F3/0659 ,  G06F3/0679 ,  G11C16/14

Abstract: A disclosed example to use an erase-suspend feature with a memory device includes sending, by a memory host controller, an erase-suspend enable setting and an erase segment duration value to the memory device. The erase-suspend enable setting is to cause the memory device to perform an erase operation as a plurality of erase segments and to suspend the erase operation between the erase segments. The erase segment duration value is to specify a length of time for the erase segments. The memory host controller initiates an erase operation to be performed at the memory device. When the erase operation is suspended, the memory host controller initiates a second memory operation to be performed at the memory device. After the memory host controller determines that the second memory operation is complete, the memory host controller initiates resumption of the erase operation.

公开(公告)号：US20220101927A1

公开(公告)日：2022-03-31

申请号：US17033082

申请日：2020-09-25

Applicant: Intel Corporation

Inventor： Aliasgar S. Madraswala ,  Sagar Upadhyay ,  Jiantao Zhou

IPC: G11C16/26 ,  G11C16/10 ,  G11C16/34

Abstract: Systems, apparatuses and methods may provide for technology that resumes a program operation with respect to NAND memory during a first tier in response to a suspension counter reaching a first threshold and resumes the program operation with respect to the NAND memory during a second tier in response to the suspension counter reaching a second threshold. The technology may also resume the program operation with respect to the NAND memory during a third tier in response to the suspension counter reaching a third threshold. Additionally, the technology may service one or more read operations with respect to the NAND memory until the suspension counter reaches the first threshold during the first tier, until the suspension counter reaches the second threshold during the second tier, and until the suspension counter reaches the third threshold during the third tier.

公开(公告)号：US11163480B2

公开(公告)日：2021-11-02

申请号：US16777812

申请日：2020-01-30

Applicant: Intel Corporation

Inventor： Aliasgar S. Madraswala ,  Kristopher H. Gaewsky ,  Siddhanth Munukutla ,  Tanya Wanchoo ,  Heonwook Kim

IPC: G06F3/06 ,  G11C16/14 ,  G11C16/04

Abstract: Embodiments of the present disclosure are directed towards techniques and configurations for a memory apparatus configured with an erase command comprising a sequence of segments. In one embodiment, the memory apparatus is configured to generate an erase command in response to a request provided by a host to erase at least a portion of data stored in a memory device. The erase command comprises a sequence of erase segments that provide an erase voltage for erasing the portion of data stored in the memory apparatus. The memory apparatus is configured to grant access to the memory apparatus for servicing the memory access requests initiated by the host, during a time period between at least two adjacent erase segments in the sequence. Other embodiments may be described and/or claimed.

公开(公告)号：US20210240380A1

公开(公告)日：2021-08-05

申请号：US16777812

申请日：2020-01-30

Applicant: Intel Corporation

Inventor： Aliasgar S. Madraswala ,  Kristopher H. Gaewsky ,  Siddhanth Munukutla ,  Tanya Wanchoo ,  Heonwook Kim

IPC: G06F3/06 ,  G11C16/14 ,  G11C16/04

Abstract: Embodiments of the present disclosure are directed towards techniques and configurations for a memory apparatus configured with an erase command comprising a sequence of segments. In one embodiment, the memory apparatus is configured to generate an erase command in response to a request provided by a host to erase at least a portion of data stored in a memory device. The erase command comprises a sequence of erase segments that provide an erase voltage for erasing the portion of data stored in the memory apparatus. The memory apparatus is configured to grant access to the memory apparatus for servicing the memory access requests initiated by the host, during a time period between at least two adjacent erase segments in the sequence. Other embodiments may be described and/or claimed.

公开(公告)号：US10956081B2

公开(公告)日：2021-03-23

申请号：US16388761

申请日：2019-04-18

Applicant: INTEL CORPORATION

Inventor： David J. Pelster ,  David B. Carlton ,  Mark Anthony Golez ,  Xin Guo ,  Aliasgar S. Madraswala ,  Sagar S. Sidhpura ,  Sagar Upadhyay ,  Neelesh Vemula ,  Yogesh B. Wakchaure ,  Ye Zhang

IPC: G06F3/06

Abstract: A data structure is maintained for performing a program operation that is allowed to be suspended to perform reads in a NAND device, where the data structure indicates a plurality of tiers, where each tier of the plurality of tiers has a number of allowed suspends of the program operation while executing in the tier, and where a sum of the number of allowed suspends for all tiers of the plurality of tiers equals a maximum allowed number of suspends of the program operation. In response to performing a resume of the program operation, after performing a read following a suspend of the program operation, a determination is made of a tier of the plurality of tiers for the program operation and a subsequent suspend of the program operation is performed only after a measure of progress of the program operation has been exceeded in the determined tier.

公开(公告)号：US10714186B2

公开(公告)日：2020-07-14

申请号：US16291142

申请日：2019-03-04

Applicant: Intel Corporation

Inventor： Purval Shyam Sule ,  Aliasgar S. Madraswala ,  Shantanu R. Rajwade ,  Trupti Ramkrishna Bemalkhedkar ,  Leonard Aaron Turcios ,  Kristopher H. Gaewsky

IPC: G11C7/02 ,  G11C16/12 ,  G11C11/56 ,  G11C16/10 ,  G11C16/34 ,  G11C16/04

Abstract: In one embodiment, an apparatus comprises a memory comprising a first group of memory cells, a second group of memory cells, and a controller to program one or more lower pages of data to the first group of memory cells; store dynamic start voltage information, the dynamic start voltage information indicative of a rate of programming of at least a portion of the first group of memory cells; determine a start program voltage based on the dynamic start voltage information; and apply the start program voltage to the second group of memory cells during a first program pass of a program operation, the program operation to program one or more lower pages of data to the second group of memory cells.